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PRELIMINARY
ElanTMSC300
Highly Integrated, Low-Power, 32-Bit Microcontroller
DISTINCTIVE CHARACTERISTICS
n Highly integrated, single-chip CPU and system logic - Optimized for embedded PC applications - Combines 32 bit, x86 compatible, low-voltage CPU with memory controller, PC/AT peripheral controllers, real-time clock, and PLL clock generators - 0.7 micron, low-voltage, CMOS process, fully static n Enhanced Am386(R) SXLV CPU core - 25 MHz or 33 MHz operating frequencies - 3.3 V core, 3.3 V or 5 V memory and I/O - Low-power, fully static design for long battery life - System Management Mode (SMM) for power management control n Integrated power management functions - Internal clock generators (using multiple PhaseLocked Loops and one external 32-KHz crystal) - Supports CPU System Management Mode (SMM) - Multiple operating modes: High Speed PLL, Low Speed PLL, Doze, Sleep, Suspend, and Off. Fully static design allows stopped clock. - Comprehensive control of system and peripheral clocks - Five external power management control pins - Suspend refresh of DRAM array - Clock switching during ISA cycles - Low power consumption: 0.12 mW typical Suspend mode power - Simultaneous multiple-voltage I/O pads operate at either 3.3 V or 5 V. Core operates at 3.3 V for minimum power consumption. n Integrated memory controller - Controls symmetrically addressable DRAM or asymmetrical 512 Kbyte x 8 bit or 1 Mbyte x 16 bit DRAM or SRAM as main memory - Zero wait-state access with 70 ns, Page mode DRAMs - Supports up to 16 Mbyte system memory - Supports up to 16 Mbyte of application ROM/ Flash, and 320 Kbyte direct ROM BIOS access. Also supports shadow RAM - Fully PC/AT compatible n Integrated PC/AT-compatible peripheral logic - One programmable interval timer (fully 8254 compatible) - Two programmable interrupt controllers (8259A compatible) - Two DMA controllers (8237A compatible) - Built-in real-time clock (146818A compatible), with an additional 114 bytes of RAM - Internal Phase-Locked Loops (PLL) generate all clocks from single 32.768 kHz crystal input n Bus configurations - 16-bit data path - Optional bus configurations: -- Internal LCD controller with subset ISA -- 386 Local Bus mode with subset ISA -- Maximum ISA Bus mode - Four programmable chip selects - Built-in 8042 chip select n Serial port controller (16450 UART compatible) n Bidirectional parallel port with EPP n Integrates two PCMCIA Version 2.1 slots n Integrated CGA-compatible LCD controller - Fully 6845 compatible - 16 gray levels in Text mode; 2 or 4 levels in Graphics mode - Supports the following LCD Panel Sizes: -- 320 x 240 single scan (2 bpp) -- 640 x 200 single/dual scan (1 bpp) -- 480 x 320 single scan (1 bpp)
This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this product without notice.
Publication# 18514 Rev: D Amendment/0 Issue Date: October 1997
PRELIMINARY
GENERAL DESCRIPTION
The ELANSC300 microcontroller is a highly integrated, low-voltage, single-chip implementation of the Am386SXLV microprocessor plus most of the additional logic needed for an AT-compatible personal computer. It is ideal for embedded PC applications, such as point-of-sale equipment, web appliances, industrial controls, and communication equipment. The ELANSC300 microcontroller from AMD is part of the growing Elan family of mobile computing products, which leverage existing AMD core modules. The ELANSC300 microcontroller demonstrates the feasibility of constructing highly integrated components built from standard cores and getting these products to market quickly. The ELANSC300 microcontroller does this by combining an Am386SXLV low-voltage microprocessor core with a memory control unit, a Power Management Unit (PMU), and the bus control and peripheral control logic of a PC/AT-compatible computer. For more information about the Am386 microprocessors, see the Am386(R)SX/SXL/SXLV Data Sheet, order #21020 and the Am386(R)DX/DXL Data Sheet, order #21017. For more information about the ElanSC310 microcontroller, see the ElanTMSC300 Microcontroller Programmer's Reference Manual, order #18470. The ELANSC300 microcontroller includes a memory controller that supports up to 16 Mbyte of DRAM, Flash or ROM; power management functions; a bus controller that supports local or ISA bus; a serial port controller that is 16450 UART compatible; a bidirectional EPPcompliant parallel port; a 146818A-compatible real-time clock; internal phase-locked loops for clock generation; and standard PC logic chips (8259A, 8237A, and 8254). The ELANSC300 microcontroller's true static design and low operating voltage enable battery-powered operation and lower weight for embedded PC applications. The internal core of the ELANSC300 microcontroller operates at 3.3 V and the I/O pads allow either 3.3 V or 5 V operation. Lowering typical operating voltage from 5 V to 3.3 V can dramatically reduce power consumption. Functionally, the ELANSC300 microcontroller is a 100% DOS/Windows-compatible, PC/AT-compatible computer on a chip that is designed to furnish the customer with a high-performance, low-power system solution, providing state-of-the-art power management in a small physical footprint. The ELANSC300 microcontroller is available in both 25and 33-MHz versions, in a 208-lead Plastic Shrink Quad Flat Pack (QFP) (PQR package) and a 208-lead Thin Quad Flat Pack (TQFP) (PQL package).
Note: Unless specified otherwise, the timings in this data sheet are based on the 33-MHz version of the ELANSC300 microcontroller.
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
CUSTOMER SERVICE
The AMD customer service network includes U.S. offices, international offices, and a customer training center. Expert technical assistance is available from the AMD worldwide staff of field application engineers and factory support staff who can answer E86 family hardware and software development questions. Hotline and World Wide Web Support For answers to technical questions, AMD provides a toll-free number for direct access to our corporate applications hotline. Also available is the AMD World Wide Web home page and FTP site, which provides the latest E86 family product information. Corporate Applications Hotline (800) 222-9323 44-(0) 1276-803-299 Toll-free for U.S. and Canada U.K. and Europe hotline World Wide Web Home Page and FTP Site To ac c es s the AM D ho me pag e, g o t o ht tp:/ / www.amd.com. Questions, requests, and input concerning AMD's WWW pages can be sent via E-mail to webmaster@amd.com. To d own lo ad do cu me nt s a nd s oft war e , ft p t o ftp.amd.com and log on as anonymous using your e-mail address as a password. Or via your web browser, go to ftp://ftp.amd.com. Documentation and Literature Free E86 family information such as data books, user's man ual s , data sh eets , ap pl ic ati on n otes , th e FusionE86 Partner Solutions Catalog, and other literature is available with a simple phone call. Internationally, contact your local AMD sales office for complete E86 family literature. Literature Ordering (800) 222-9323 (512) 602-5651 Toll-free for U.S. and Canada Direct dial worldwide
ElanTMSC300 Microcontroller Data Sheet
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PRELIMINARY
BLOCK DIAGRAM
SA12-SA0 IOR, IOW, MEMR, MEMW, BALE D15-D0
DSMA14-DSMA0 DSMD7-DSMD0 LCD Interface
A20GATE, RC 8042CS, SYSCLK
MCS16, IOCS16, IOCHRDY, 0WS
DACKx, TC, AEN DREQx LCD Controller
A23-A13, ADS, D/C,M/IO, W/R, BHE, BLE, CPUCLK, CPURST, CPURDY
Bus Controller
DMA Controller (2x8237A-5)
Local Bus Controller
LRDY, LDEV
Memory Controller PD15-PD0 Am386SXLV PA23-PA0 CONTROL
RAS, CAS, MWE
M U X
MA11/SA12- MA0/SA23
LFX X32IN Power Management Control Unit PMCx ACIN, BLx, EXTSMI, SUS/RES
Mapping Registers
PGP3-PGP0
Clock Generators
Parallel Port Control
PPDWE, PPOEN AFDT, STRB, SLCT, INIT ACK, BUSY, ERROR, PE, SLCT
X32OUT Serial Port (16450) Real-Time Clock (146818A) DTR, RTS, SOUT CTS, DSR, DCD, SIN, RIN
MCEL, MCEH, VPP, REG CD, RDY, WP, BVDx Programmable Interval Timer (8254) Interrupt Controller (2x8259) PCMCIA Interface MCEL, MCEH, VPP, REG CD, RDY, WP, BVDx
} SLOT A } SLOT B
WAIT (common) IRQx
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
ORDERING INFORMATION
AMD standard products are available in several packages and operating ranges. The order numbers (Valid Combinations) are formed by a combination of the elements below.
ELANSC300
-25
K
C
TEMPERATURE RANGE C = Commercial (0C TAMBIENT 70C) I = Industrial (-40C < TCASE 85C) PACKAGE TYPE K = 208 lead QFP (Plastic Shrink Quad Flat Pack) (PQR-208) V = 208 lead TQFP (Thin Quad Flat Pack) (PQL-208) SPEED OPTION -25 = 25 MHz -33 = 33 MHz DEVICE NUMBER/DESCRIPTION ELANSC300 microcontroller Highly integrated, low-power, 32-bit microprocessor and system logic
Valid Combinations ELANSC300-25 ELANSC300-33 ELANSC300-25 ELANSC300-33 ELANSC300-25 ELANSC300-33 KC KC KI KI VC VC
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
ElanTMSC300 Microcontroller Data Sheet
5
PRELIMINARY
TABLE OF CONTENTS
Distinctive Characteristics ............................................................................................................ 1 General Description ..................................................................................................................... 2 Customer Service ........................................................................................................................ 3 Block Diagram ............................................................................................................................. 4 Ordering Information .................................................................................................................... 5 Connection Diagram .................................................................................................................. 13 ELANSC300 Microcontroller Pin Designations ............................................................................ 14 Pin Designations (Sorted by Pin Number) ................................................................................. 15 Pin Designations (Sorted by Pin Name) .................................................................................... 17 Pin State Tables ........................................................................................................................ 24 Pin Characteristics ................................................................................................................ 24 Pin Descriptions ......................................................................................................................... 34 Memory Bus Interface................................................................................................................ 34 CAS1H [SRCS3], CAS1L [SRCS2], CAS0H [SRCS1], CAS0L [SRCS0] ............................. 34 DOSCS ................................................................................................................................. 34 MA11-MA0/SA23-SA12....................................................................................................... 34 MWE ..................................................................................................................................... 34 RAS1-RAS0 ......................................................................................................................... 34 ROMCS................................................................................................................................. 34 System Interface ........................................................................................................................ 35 AEN [TDI] .............................................................................................................................. 35 D15-D0 ................................................................................................................................. 35 DACK2 [TCK] ........................................................................................................................ 35 DBUFOE ............................................................................................................................... 35 DRQ2 [TDO].......................................................................................................................... 35 ENDIRH ................................................................................................................................ 35 ENDIRL ................................................................................................................................. 35 IOCHRDY.............................................................................................................................. 35 IOCS16 [LCDDL0]................................................................................................................. 35 IOR........................................................................................................................................ 35 IOW ....................................................................................................................................... 36 IRQ1, IRQ14 [LCDDL2]......................................................................................................... 36 MCS16 [LCDDL1] ................................................................................................................. 36 MEMR ................................................................................................................................... 36 MEMW .................................................................................................................................. 36 PIRQ0 (PIRQ0/IRQ3), PIRQ1 (PIRQ1/IRQ6) ....................................................................... 36 RSTDRV ............................................................................................................................... 36 SA11-SA0............................................................................................................................. 36 SBHE [LCDDL3].................................................................................................................... 36 SPKR .................................................................................................................................... 36 TC [TMS]............................................................................................................................... 37 Keyboard Interface .................................................................................................................... 37 8042CS [XTDAT] .................................................................................................................. 37 A20GATE .............................................................................................................................. 37 RC ......................................................................................................................................... 37 SYSCLK [XTCLK] ................................................................................................................. 37 Parallel Port Interface ................................................................................................................ 37 ACK....................................................................................................................................... 37 AFDT [X14OUT].................................................................................................................... 37 BUSY .................................................................................................................................... 37 ERROR ................................................................................................................................. 37 INIT [PCMCWE] .................................................................................................................... 37
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
PE ......................................................................................................................................... 37 PPDWE [PPDCS].................................................................................................................. 37 PPOEN.................................................................................................................................. 37 SLCT ..................................................................................................................................... 37 SLCTIN [PCMCOE]............................................................................................................... 38 STRB..................................................................................................................................... 38 Serial Port Interface ................................................................................................................... 38 CTS ....................................................................................................................................... 38 DCD ...................................................................................................................................... 38 DSR....................................................................................................................................... 38 DTR/CFG1 ............................................................................................................................ 38 RIN ........................................................................................................................................ 38 RTS/CFG0 ............................................................................................................................ 38 SIN ........................................................................................................................................ 38 SOUT .................................................................................................................................... 38 PCMCIA Interface ...................................................................................................................... 38 BVD1_A (STSCHG_A), BVD1_B (STSCHG_B) ................................................................... 38 BVD2_A (SPKR_A), BVD2_B (SPKR_B) ............................................................................. 38 CA24 ..................................................................................................................................... 38 CA25 ..................................................................................................................................... 38 CD_A, CD_B ......................................................................................................................... 38 ICDIR .................................................................................................................................... 39 MCEH_A, MCEH_B .............................................................................................................. 39 MCEL_A, MCEL_B ............................................................................................................... 39 PCMCOE .............................................................................................................................. 39 PCMCWE.............................................................................................................................. 39 RDY_A (IREQ_A), RDY_B (IREQ_B) ................................................................................... 39 REG_A, REG_B.................................................................................................................... 39 RST_A, RST_B ..................................................................................................................... 39 VPP_A, VPP_B ..................................................................................................................... 39 WAIT_AB .............................................................................................................................. 39 WP_A (IOIS16A), WP_B (IOIS16B)...................................................................................... 39 Power Management Interface .................................................................................................... 40 ACIN...................................................................................................................................... 40 BL4-BL1 ............................................................................................................................... 40 EXTSMI................................................................................................................................. 40 LPH ....................................................................................................................................... 40 PGP3-PGP0 ......................................................................................................................... 40 PMC4-PMC0 ........................................................................................................................ 40 SUS/RES .............................................................................................................................. 40 Display Interface ........................................................................................................................ 40 CP1 ....................................................................................................................................... 41 CP2 ....................................................................................................................................... 41 DSCE .................................................................................................................................... 41 DSMA14-DSMA0 ................................................................................................................. 41 DSMD7-DSMD0 ................................................................................................................... 41 DSOE .................................................................................................................................... 41 DSWE ................................................................................................................................... 41 FRM ...................................................................................................................................... 41 LCDD0 .................................................................................................................................. 41 LCDD1 .................................................................................................................................. 41 LCDD2 .................................................................................................................................. 41 LCDD3 .................................................................................................................................. 41
ElanTMSC300 Microcontroller Data Sheet
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PRELIMINARY
[LCDDL3-LCDDL0]............................................................................................................... 41 LVDD..................................................................................................................................... 41 LVEE ..................................................................................................................................... 41 M ........................................................................................................................................... 42 Miscellaneous Interface ............................................................................................................. 42 LF1, LF2, LF3, LF4 (Analog inputs) ...................................................................................... 42 X1OUT [BAUD_OUT]............................................................................................................ 42 [X14OUT] .............................................................................................................................. 42 X32IN, X32OUT .................................................................................................................... 42 Local Bus Interface .................................................................................................................... 42 A23-A12 ............................................................................................................................... 42 ADS....................................................................................................................................... 42 BHE....................................................................................................................................... 42 BLE ....................................................................................................................................... 42 CPUCLK................................................................................................................................ 43 CPURDY ............................................................................................................................... 43 CPURST ............................................................................................................................... 43 D/C ........................................................................................................................................ 43 LDEV..................................................................................................................................... 43 LRDY..................................................................................................................................... 43 M/IO ...................................................................................................................................... 43 W/R ....................................................................................................................................... 43 Maximum ISA Bus Interface ...................................................................................................... 43 0WS ...................................................................................................................................... 43 BALE ..................................................................................................................................... 43 DACK7, DACK6, DACK5, DACK3, DACK2, DACK1, DACK0 .............................................. 43 DRQ7, DRQ6, DRQ5, DRQ3, DRQ2, DRQ1, DRQ0 ............................................................ 43 IOCHCHK.............................................................................................................................. 43 IRQ15, IRQ14, IRQ12-IRQ9, IRQ7-IRQ3, IRQ1 ................................................................. 44 LA23-LA17 ........................................................................................................................... 44 LMEG .................................................................................................................................... 44 JTAG Boundary Scan Interface ................................................................................................. 44 JTAGEN ................................................................................................................................ 44 [TCK] ..................................................................................................................................... 44 [TDI] ...................................................................................................................................... 44 [TDO]..................................................................................................................................... 44 [TMS]..................................................................................................................................... 44 Reset and Power ....................................................................................................................... 44 AGND.................................................................................................................................... 44 AVCC .................................................................................................................................... 44 GND ...................................................................................................................................... 45 IORESET .............................................................................................................................. 45 RESIN ................................................................................................................................... 45 VCC....................................................................................................................................... 45 VCC1..................................................................................................................................... 45 VCC5..................................................................................................................................... 45 VMEM ................................................................................................................................... 45 VSYS..................................................................................................................................... 45 VSYS2................................................................................................................................... 45 Functional Description ............................................................................................................... 45 Am386SXLV CPU Core ........................................................................................................ 45 Memory Controller ................................................................................................................. 46 SRAM .................................................................................................................................... 49
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
PCMCIA Slots ....................................................................................................................... 50 The PMU Modes and Clock Generators ............................................................................... 50 ELANSC300 Microcontroller Power Management .................................................................. 53 Micro Power Off Mode .......................................................................................................... 55 Core Peripheral Controllers ................................................................................................... 60 Additional Peripheral Controllers ........................................................................................... 60 Parallel Port Anomalies ......................................................................................................... 62 PC/AT Support Features ....................................................................................................... 62 LCD, Local Bus, or Maximum ISA Bus Controller ................................................................. 65 Alternate Pin Functions .............................................................................................................. 68 CPU Local Bus Interface versus Internal LCD Interface ....................................................... 69 Maximum ISA Interface versus Internal LCD Interface ......................................................... 70 Alternate Pin Functions Selected Via Firmware ........................................................................ 71 SRAM Interface ..................................................................................................................... 71 Dual-Scan LCD Data Bus ..................................................................................................... 71 Unidirectional/Bidirectional Parallel Port ............................................................................... 71 X1OUT [BAUD_OUT] Clock Source ..................................................................................... 72 PC/XT Keyboard ................................................................................................................... 72 PCMCIA Data Path Control ................................................................................................... 72 14-MHz Clock Source ........................................................................................................... 72 ISA Bus Descriptions ................................................................................................................. 73 System Test and Debug ........................................................................................................ 74 JTAG Instruction Opcodes .................................................................................................... 79 Absolute Maximum Ratings ....................................................................................................... 80 Operating Ranges...................................................................................................................... 80 Thermal Characteristics ............................................................................................................. 82 Typical Power Numbers ............................................................................................................. 82 Derating Curves ......................................................................................................................... 84 Voltage Partitioning .................................................................................................................... 95 Crystal Specifications ................................................................................................................ 95 Loop Filters ................................................................................................................................ 97 AC Switching Characteristics and Waveforms .......................................................................... 98 AC Switching Test Waveforms .............................................................................................. 98 AC Switching Characteristics over Commercial and Industrial Operating Ranges ............... 99 Physical Dimensions ................................................................................................................ 138 PQR 208, Trimmed and Formed Plastic Shrink Quad Flat Pack (QFP) ............................. 138 PQL 208, Trimmed and Formed Thin Quad Flat Pack (TQFP) ........................................... 139
LIST OF FIGURES
Figure 1. PLL Block Diagram .................................................................................................. Figure 2. Clock Steering Block Diagram ................................................................................. Figure 3. Typical System Design with Secondary Power Supply to Maintain RTC When Primary Power Supply is Off (DRAM Refresh is Optional.) .......................... Figure 4. ELANSC300 Microcontroller I/O Structure ................................................................. Figure 5. ELANSC300 Microcontroller Unidirectional Parallel Port Data Bus Implementation......................................................................................... Figure 6. The ELANSC300 CPU Bidirectional Parallel Port and EPP Implementation ............. Figure 7. Typical System Block Diagram (Internal LCD Controller) ........................................ Figure 8. Bus Option Configuration Select .............................................................................. Figure 9. 3.3-V I/O Drive Type E Rise Time............................................................................ Figure 10. 3.3-V I/O Drive Type E Fall Time ............................................................................. Figure 11. 5-V I/O Drive Type E Rise Time............................................................................... 51 52 56 57 61 62 64 68 85 85 86
ElanTMSC300 Microcontroller Data Sheet
9
PRELIMINARY
Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56.
5-V I/O Drive Type E Fall Time ................................................................................ 86 3.3-V I/O Drive Type D Rise Time............................................................................ 87 3.3-V I/O Drive Type D Fall Time ............................................................................. 87 5-V I/O Drive Type D Rise Time............................................................................... 88 5-V I/O Drive Type D Fall Time ................................................................................ 88 3.3-V I/O Drive Type C Rise Time............................................................................ 89 3.3-V I/O Drive Type C Fall Time ............................................................................. 89 5-V I/O Drive Type C Rise Time............................................................................... 90 5-V I/O Drive Type C Fall Time ................................................................................ 90 3.3-V I/O Drive Type B Rise Time............................................................................ 91 3.3-V I/O Drive Type B Fall Time ............................................................................. 91 5-V I/O Drive Type B Rise Time............................................................................... 92 5-V I/O Drive Type B Fall Time ................................................................................ 92 3.3-V I/O Drive Type A Rise Time............................................................................ 93 3.3-V I/O Drive Type A Fall Time ............................................................................. 93 5-V I/O Drive Type A Rise Time............................................................................... 94 5-V I/O Drive Type A Fall Time ................................................................................ 94 X32 Oscillator Circuit................................................................................................ 96 Loop-Filter Component ............................................................................................ 97 Key to Switching Waveforms ................................................................................... 98 Power-Up Sequence Timing .................................................................................. 100 Micro Power Off Mode Exit .................................................................................... 100 Entering Micro Power Off Mode (DRAM Refresh Disabled) .................................. 101 Entering Micro Power Off Mode (DRAM Refresh Enabled) ................................... 101 DRAM Timings, Page Hit ....................................................................................... 103 DRAM Timings, Refresh Cycle .............................................................................. 103 DRAM First Cycle and Bank/Page Miss (Read Cycles)......................................... 105 DRAM First Cycle and Bank/Page Miss (Write Cycles) ......................................... 107 Local Bus Interface ................................................................................................ 109 Display SRAM Timings .......................................................................................... 111 LCD Interface Timings ........................................................................................... 111 PCMCIA Memory Read Cycle................................................................................ 113 PCMCIA Memory Write Cycle................................................................................ 115 PCMCIA I/O Read Cycle........................................................................................ 117 PCMCIA I/O Write Cycle ........................................................................................ 119 BIOS ROM Read/Write 8-Bit Cycle........................................................................ 121 DOS ROM Read/Write 8-Bit Cycle......................................................................... 123 DOS ROM Read/Write 16-Bit Cycle....................................................................... 125 ISA Memory Read/Write 8-Bit Cycle ...................................................................... 127 ISA Memory Read/Write 16-Bit Cycle .................................................................... 129 ISA Memory Read/Write 0 Wait State Cycle.......................................................... 131 ISA I/O 8-Bit Read/Write Cycle .............................................................................. 133 ISA I/O 16-Bit Read/Write Cycle ............................................................................ 135 EPP Data Register Write Cycle.............................................................................. 136 EPP Data Register Read Cycle ............................................................................. 137
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
LIST OF TABLES
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. I/O Pin Voltage Level................................................................................................. Memory Bus Interface ............................................................................................... System Interface ....................................................................................................... Keyboard Interface .................................................................................................... Parallel Port Interface................................................................................................ Serial Port Interface................................................................................................... Power Management Interface ................................................................................... PCMCIA Interface ..................................................................................................... Display Interface........................................................................................................ Miscellaneous Interface............................................................................................. Power Pins ................................................................................................................ Non-Multiplexed Address Signals Provided by MA11-MA0...................................... DRAM Mode Selection .............................................................................................. MA and SA Signal Pin Sharing.................................................................................. Supported DRAM/SRAM Configuration .................................................................... DRAM Address Translation (Page Mode) ................................................................. DRAM Address Translation (Enhanced Page Mode)................................................ SRAM Access Pins ................................................................................................... SRAM Wait State Select Logic.................................................................................. High-Speed CPU Clock Frequencies ........................................................................ PLL Output ................................................................................................................ PMU Modes............................................................................................................... Internal Clock States ................................................................................................. Internal I/O Pulldown States...................................................................................... Parallel Port EPP Mode Pin Definition ...................................................................... External Resistor Requirements................................................................................ Bus Option Select Bit Logic....................................................................................... Pins Shared Between CPU Local Bus and Internal LCD Interface Functions........... Pins Shared Between Maximum ISA Bus and Internal LCD Interface Functions ..... SRAM Interface ......................................................................................................... Dual-Scan LCD Data Bus.......................................................................................... Bidirectional Parallel Port Pin Description ................................................................. X1OUT Clock Source Pin Description....................................................................... XT Keyboard Pin Description .................................................................................... PCMCIA Data Path Control....................................................................................... 14-MHz Clock Source ............................................................................................... Internal LCD Controller Bus Mode ISA Bus Functionality ......................................... Local Bus Mode Additional ISA Bus Functionality..................................................... Maximum ISA Bus Mode Additional ISA Bus Functionality....................................... Boundary Scan (JTAG) Cells--Order and Type ....................................................... ELANSC300 Microcontroller JTAG Instruction Opcodes ............................................ DC Characteristics over Commercial and Industrial Operating Ranges (Plastic Shrink Quad Flat Pack (QFP), 33 MHz, 3.3 V)............................................. DC Characteristics over Commercial and Industrial Operating Ranges (Plastic Shrink Quad Flat Pack (QFP), 33 MHz, 5 V)................................................ Commercial and Industrial Operating Voltage Ranges at 25................................... Thermal Resistance (C/Watt) JT and JA for 208-pin QFP and TQFP packages .. Typical Maximum ISA Mode Power Consumption .................................................... Typical Internal LCD Mode Power Consumption ...................................................... I/O Drive Type Description (Worst Case) .................................................................. Recommended Oscillator Component Value Limits.................................................. Loop-Filter Component Values.................................................................................. 24 25 26 28 28 29 29 30 31 33 33 34 46 46 47 48 49 49 50 53 53 54 54 59 61 65 68 69 70 71 71 71 72 72 72 72 73 73 73 75 79 80 81 81 82 82 83 84 96 97
ElanTMSC300 Microcontroller Data Sheet
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PRELIMINARY
Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73.
Power-Up Sequencing ............................................................................................. 99 DRAM Memory Interface, Page Hit and Refresh Cycle ......................................... 102 DRAM First Cycle Read Access ............................................................................. 104 DRAM Bank/Page Miss Read Cycles .................................................................... 104 DRAM First Cycle Write Access ............................................................................. 106 DRAM Bank/Page Miss Write Cycles ..................................................................... 106 Local Bus Interface ................................................................................................. 108 Video RAM/LCD Interface ....................................................................................... 110 Power Management Control Signals ...................................................................... 110 PCMCIA Memory Read Cycle ................................................................................ 112 PCMCIA Memory Write Cycle ................................................................................ 114 PCMCIA I/O Read Cycle ........................................................................................ 116 PCMCIA I/O Write Cycle ........................................................................................ 118 BIOS ROM Read/Write 8-Bit Cycle ........................................................................ 120 DOS ROM Read/Write 8-Bit Cycle ......................................................................... 122 DOS ROM and Fast DOS ROM Read/Write 16-Bit Cycles .................................... 124 ISA Memory Read/Write 8-Bit Cycle ...................................................................... 126 ISA Memory Read/Write 16-Bit Cycle .................................................................... 128 ISA Memory Read/Write 0 Wait State Cycle .......................................................... 130 ISA I/O 8-Bit Read/Write Cycle .............................................................................. 132 ISA I/O 16-Bit Read/Write Cycle ............................................................................ 134 EPP Data Register Write Cycle .............................................................................. 136 EPP Data Register Read Cycle .............................................................................. 137
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ElanTMSC300 Microcontroller Data Sheet
CONNECTION DIAGRAM
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 GND RAS0 RAS1 CAS1L [SRCS2] CAS1H [SRCS3] CAS0L [SRCS0] CAS0H [SRCS1] MWE VMEM MA10/SA13 MA9/SA23 GND MA8/SA22 MA7/SA21 MA6/SA20 MA5/SA19 MA4/SA18 MA3/SA17 MA2/SA16 GND MA1/SA15 VMEM VCC MA0/SA14 D15 D14 D13 D12 D11 D10 D9 D8 GND D7 VMEM D6 D5 D4 D3 D2 D1 D0 DOSCS ROMCS SYSCLK[XTCLK] DACK2 [TCK] AEN [TDI] VSYS TC [TMS] ENDIRL ENDIRH GND
PRELIMINARY
ElanTMSC300 Microcontroller Data Sheet
GND IOR IOW MEMR MEMW RSTDRV DBUFOE MA11/SA12 SA11 SA10 SA9 SA8 VSYS SA7 SA6 GND SA5 SA4 SA3 SA2 SA1 SA0 8042CS[XTDAT] DRQ2 [TDO] PMC2 RC A20GATE AFDT[X14OUT] VCC PE STRB SLCTIN[PCMCOE] BUSY ERROR SLCT ACK INIT[PCMCWE] PPWDE [PPDCS] PPOEN DTR/CFG1 RTS/CFG0 SOUT VCC5 CTS DSR DCD SIN RIN ACIN EXTSMI SUS/RES GND GND DSMA8 (A17/LA17) DSMA9 (A18/LA18) DSMA10 (A19/LA19) DSMA11 (A20/LA20) DSMA12 (A21/LA21) DSMA13 (A22/LA22) DSMA14 (A23/LA23) DSMD0 (LDEV/RSVD) DSOE (CPURDY/LMEG) DSCE (DACK1/DACK1) LVDD(A12/BALE) LCDD0 (DACK5/DACK5) SBHE [LCDDL3] VSYS2 RESIN IORESET SPKR PMC1 PMC0 CA25 VCC CA24 RST_A REG_A VPP_A MCEH_A MCEL_A VCC5 RST_B REG_B VPP_B MCEH_B MCEL_B ICDIR GND BVD1_B BVD2_B WP_B RDY_B CD_B WAIT_AB BVD1_A BVD2_A WP_A RDY_A CD_A BL4 BL3 BL2 BL1 GND 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
AGND LF4 Video PLL LF3 Low Speed PLL LF2 Internal PLL LF1 High Speed PLL AVCC X32OUT X32IN X1OUT [BAUD OUT] JTAGEN IRQ14 [LCDDL2] MCS16 [LCDDL1] IOCS16 [LCDDL0] IRQ1 PIRQ0 (PIRQ0/IRQ3) PIRQ1 (PIRQ1/IRQ6) IOCHRDY GND LPH PGP0 PGP1 PGP2 PGP3 PMC3 PMC4 DSWE (PULLUP/PULLUP) LVEE (IRQ15/IRQ5) FRM (IRQ12/IRQ12) VCC CP2 (PULLUP/IRQ10) CP1 (PULLDN/IRQ15) LCDD2 (IOCHCHK/IOCHCHK) VCC1 LCDD1 (DRQ5/DRQ5) LCDD3 (DRQ1/DRQ1) M (IRQ4/IRQ4) DSMD7 (ADS/0WS) DSMD6 (D/C/DRQ0) DSMD5 (M/IO/DRQ3) DSMD4 (W/R/DRQ7) DSMD3 (BHE/IRQ9) DSMD2 (BLE/IRQ11) DSMD1 (LRDY/DRQ6) DSMA0 (NC/PULLUP) DSMA1(PULLUP/IRQ7) DSMA2 (CPURST/RESERVED) DSMA3 (CPUCLK/PULLUP) DSMA4 (A13/DACK6) DSMA5 (A14/DACK7) DSMA6 (A15/DACK3) DSMA7 (A16/DACK0) GND
13
PRELIMINARY
ELANSC300 MICROCONTROLLER PIN DESIGNATIONS
This section, beginning with the Connection Diagram on the preceding page, identifies the pins of the ELANSC300 microcontroller and lists the signals associated with each pin. The table beginning on page 15 lists the pins sorted by pin number; the table beginning on page 17 lists the pins sorted by pin name along with the corresponding pin number, functional grouping, Pin State table number, and the page number where a description of the pin is located. Tables 2-11, beginning on page 25, group these signals according to function. The Signal Name column in the pin designation table (sorted by pin number), and in Tables 2-11, is decoded as follows: NAME3 - This is a tertiary pin function that must be enabled specifically by firmware. As an example, for pins DACK2[TCK], DRQ2[TDO], AEN[TDI], and TC[TMS], the NAME3 function is selected by the JTAGEN pin being asserted High (JTAG ENABLE). NAME4 - Designates the pin function when the ELANSC300 microcontroller has been configured, at reset, for the Local Bus mode of operation. NAME5 - Designates the pin function when the ELANSC300 microcontroller has been configured, at reset, for the Maximum ISA mode of operation. RSVD - Pins marked with this designator are required to remain unconnected. PULLUP - Needs external pull-up resistor. PULLDN - Needs external pull-down resistor. NAME1 - This is the pin function when the ELANSC300 microcontroller has been configured, at reset, for the internal LCD Controller mode of operation. If the pin only has one function regardless of the mode, NAME1 is the only name given. NAME2 - This is the secondary pin function (by default) when the ELANSC300 microcontroller has been configured, at reset, for the internal LCD Controller mode of operation. If the pin always has two functions regardless of the mode, NAME1 followed by NAME2 are the only names given. The Signal Name column in the pin designation table (sorted by pin name), beginning on page 17, contains an alphabetical listing of all pin names, followed by their corresponding alternate pin names in the applicable format from those listed here:
NAME1 / NAME2 [NAME3] (NAME4 / NAME5)
NAME1 / NAME2 [NAME3] (NAME4 / NAME5) NAME2 / NAME1 [NAME3] (NAME4 / NAME5) [NAME3] (NAME4 / NAME5) NAME1 / NAME2 (NAME4 / NAME5) NAME1 / NAME2 [NAME3] (NAME5 / NAME4) NAME1 / NAME2 [NAME3]
For more information about how pins are shared and which functions are available in each bus mode, see "Alternate Pin Functions" on page 68.
14
ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
PIN DESIGNATIONS (SORTED BY PIN NUMBER)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Signal Name (Alternate Functions) GND RAS0 RAS1 CAS1L [SRCS2] CAS1H [SRCS3] CAS0L [SRCS0] CAS0H [SRCS1] MWE VMEM MA10/SA13 MA9/SA23 GND MA8/SA22 MA7/SA21 MA6/SA20 MA5/SA19 MA4/SA18 MA3/SA17 MA2/SA16 GND MA1/SA15 VMEM VCC MA0/SA14 D15 D14 D13 D12 D11 D10 D9 D8 GND D7 VMEM D6 D5 D4 D3 D2 D1 D0 DOSCS Pin No. 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 Signal Name (Alternate Functions) ROMCS SYSCLK [XTCLK] DACK2 [TCLK] AEN [TDI] VSYS TC [TMS] ENDIRL ENDIRH GND GND IOR IOW MEMR MEMW RSTDRV DBUFOE MA11/SA12 SA11 SA10 SA9 SA8 VSYS SA7 SA6 GND SA5 SA4 SA3 SA2 SA1 SA0 8042CS [XTDAT] DRQ2 [TDO] PMC2 RC A20GATE AFDT [X14OUT] VCC PE STRB SLCTIN [PCMCOE] BUSY ERROR Pin No. 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 Signal Name (Alternate Functions) SLCT ACK INIT [PCMCWE] PPDWE [PPDCS] PPOEN DTR/CFG1 RTS/CFG0 SOUT VCC5 CTS DSR DCD SIN RIN ACIN EXTSMI SUS/RES GND GND BL1 BL2 BL3 BL4 CD_A RDY_A WP_A BVD2_A BVD1_A WAIT_AB CD_B RDY_B WP_B BVD2_B BVD1_B GND ICDIR MCEL_B MCEH_B VPP_B REG_B RST_B VCC5 MCEL_A
ElanTMSC300 Microcontroller Data Sheet
15
PRELIMINARY
PIN DESIGNATIONS (SORTED BY PIN NUMBER) (CONTINUED)
Pin No. 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 Signal Name (Alternate Functions) MCEH_A VPP_A REG_A RST_A CA24 VCC CA25 PMC0 PMC1 SPKR IORESET RESIN VSYS2 SBHE [LCDDL3] LCDD0 (DACK5/DACK5) LVDD (A12/BALE) DSCE (DACK1/ DACK1) DSOE (CPURDY/LMEG) DSMD0 (LDEV/RSVD) DSMA14 (A23/LA23) DSMA13 (A22/LA22) DSMA12 (A21/LA21) DSMA11 (A20/LA20) DSMA10 (A19/LA19) DSMA9 (A18/LA18) DSMA8 (A17/LA17) GND Pin No. 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 Signal Name (Alternate Functions) GND DSMA7 (A16/DACK0) DSMA6 (A15/DACK3) DSMA5 (A14/DACK7) DSMA4 (A13/DACK6) DSMA3 (CPUCLK/PULLUP) DSMA2 (CPURST/RSVD) DSMA1 (PULLUP/IRQ7) DSMA0 (NC/PULLUP) DSMD1 (LRDY/DRQ6) DSMD2 (BLE/IRQ11) DSMD3 (BHE/IRQ9) DSMD4 (W/R/DRQ7) DSMD5 (M/IO/DRQ3) DSMD6 (D/C/DRQ0) DSMD7 (ADS/0WS) M (IRQ4/IRQ4) LCDD3 (DRQ1/DRQ1) LCDD1 (DRQ5/DRQ5) VCC1 LCDD2 (IOCHCHK/ IOCHCHK) CP1 (PULLDN/IRQ5) CP2 (PULLUP/IRQ10) VCC FRM (IRQ12/IRQ12) LVEE (IRQ15/IRQ15) DSWE (PULLUP/PULLUP) Pin No. 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Signal Name (Alternate Functions) PMC4 PMC3 PGP3 PGP2 PGP1 PGP0 LPH GND IOCHRDY PIRQ1 (PIRQ1/IRQ6) PIRQ0 (PIRQ0/IRQ3) IRQ1 IOCS16 [LCDDL0] MCS16 [LCDDL1] IRQ14 [LCDDL2] JTAGEN X1OUT [BAUD_OUT] X32IN X32OUT AVCC LF1 LF2 LF3 LF4 AGND -
16
ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
PIN DESIGNATIONS (SORTED BY PIN NAME)
Signal Name (Alternate Functions) (0WS/ADS) DSMD7 8042CS [XTDAT] (A12/BALE) LVDD (A13/DACK6) DSMA4 (A14/DACK7) DSMA5 (A15/DACK3) DSMA6 (A16/DACK0) DSMA7 (A17/LA17) DSMA8 (A18/LA18) DSMA9 (A19/LA19) DSMA10 (A20/LA20) DSMA11 A20GATE (A21/LA21) DSMA12 (A22/LA22) DSMA13 (A23/LA23) DSMA14 ACIN ACK (ADS/0WS) DSMD7 AEN [TDI] AFDT [X14OUT] AGND AVCC (BALE/A12) LVDD [BAUD_OUT] X1OUT (BHE/IRQ9) DSMD3 BL1 BL2 BL3 BL4 (BLE/IRQ11) DSMD2 BUSY BVD1_A (STSCHG_A) BVD1_B (STSCHG_B) BVD2_A (SPKR_A) BVD2_B (SPKR_B) CA24 CA25 CAS0H [SRCS1] CAS0L [SRCS0] CAS1H [SRCS3] CAS1L [SRCS2] CD_A Pin No. 172 75 173 161 160 159 158 155 154 153 152 79 151 150 149 101 88 172 47 80 208 203 173 200 168 106 107 108 109 167 85 114 120 113 119 134 136 7 6 5 4 110 Functional Group Maximum ISA bus interface Keyboard interface Local bus interface Local bus interface Local bus interface Local bus interface Local bus interface Local bus interface Local bus interface Local bus interface Local bus interface Keyboard interface Local bus interface Local bus interface Local bus interface Power management interface Parallel port interface Local bus interface System interface Parallel port interface Power Power Maximum ISA bus interface Miscellaneous interface Local bus interface Power management interface Power management interface Power management interface Power management interface Local bus interface Parallel port interface PCMCIA interface PCMCIA interface PCMCIA interface PCMCIA interface PCMCIA interface PCMCIA interface Memory bus interface Memory bus interface Memory bus interface Memory bus interface PCMCIA interface Pin State Table Number 8 3 8 8 8 8 8 8 8 8 8 3 8 8 8 6 4 8 2 4 10 10 8 9 8 6 6 6 6 8 4 7 7 7 7 7 7 1 1 1 1 7 Description Page Number 43 37 42 42 42 42 42 42 42 42 42 37 42 42 42 40 37 42 35 37 44 44 43 42 42 40 40 40 40 42 37 38 38 38 38 38 38 34 34 34 34 38
ElanTMSC300 Microcontroller Data Sheet
17
PRELIMINARY
PIN DESIGNATIONS (SORTED BY PIN NAME) (CONTINUED)
Signal Name (Alternate Functions) CD_B CFG0/RTS CFG1/DTR CP1 (PULLDN/IRQ5) CP2 (PULLUP/IRQ10) (CPUCLK/PULLUP) DSMA3 (CPURDY/LMEG) DSOE (CPURST/RSVD) DSMA2 CTS D0 D1 D10 D11 D12 D13 D14 D15 D2 D3 D4 D5 D6 D7 D8 D9 (DACK0/A16) DSMA7 (DACK1/DACK1) DSCE DACK2 [TCK] (DACK3/A15) DSMA6 (DACK5/DACK5) LCDD0 (DACK6/A13) DSMA4 (DACK7/A14) DSMA5 DBUFOE (D/C/DRQ0) DSMD6 DCD DOSCS (DRQ0/D/C) DSMD6 (DRQ1/DRQ1) LCDD3 DRQ2 [TDO] (DRQ3/M/IO) DSMD5 (DRQ5/DRQ5) LCCD1 (DRQ6/LRDY) DSMD1 (DRQ7/W/R) DSMD4 Pin No. 116 93 92 178 179 162 147 163 96 42 41 30 29 28 27 26 25 40 39 38 37 36 34 32 31 158 146 46 159 144 161 160 59 171 98 43 171 174 76 170 175 166 169 Functional Group PCMCIA interface Serial port interface Serial port interface Display interface Display interface Local bus interface Local bus interface Local bus interface Serial port interface System interface System interface System interface System interface System interface System interface System interface System interface System interface System interface System interface System interface System interface System interface System interface System interface Maximum ISA bus interface Local and maximum ISA bus interface System and maximum ISA bus interface Maximum ISA bus interface Local and maximum ISA bus interface Maximum ISA bus interface Maximum ISA bus interface System interface Local bus interface Serial port interface Memory bus interface Maximum ISA bus interface Local and maximum ISA bus interface System and maximum ISA bus interface Maximum ISA bus interface Local and maximum ISA bus interface Maximum ISA bus interface Maximum ISA bus interface Pin State Table Number 7 5 5 8 8 8 8 8 5 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 8 8 2 8 8 8 8 2 8 5 1 8 8 2 8 8 8 8 Description Page Number 38 38 38 41 41 43 43 43 38 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 43 43 35, 44 43 43 43 43 35 43 38 34 43 43 35, 44 43 43 43 43
18
ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
PIN DESIGNATIONS (SORTED BY PIN NAME) (CONTINUED)
Signal Name (Alternate Functions) DSCE (DACK1/DACK1) DSMA0 (NC/PULLUP) DSMA1 (PULLUP/IRQ7) DSMA10 (A19/LA19) DSMA11 (A20/LA20) DSMA12 (A21/LA21) DSMA13 (A22/LA22) DSMA14 (A23/LA23) DSMA2 (CPURST/RSVD) DSMA3 (CPUCLK/PULLUP) DSMA4 (A13/DACK6) DSMA5 (A14/DACK7) DSMA6 (A15/DACK3) DSMA7 (A16/DACK0) DSMA8 (A17/LA17) DSMA9 (A18/LA18) DSMD0 (LDEV/RSVD) DSMD1 (LRDY/DRQ6) DSMD2 (BLE/IRQ11) DSMD3 (BHE/IRQ9) DSMD4 (W/R/DRQ7) DSMD5 (M/IO/DRQ3) DSMD6 (D/C/DRQ0) DSMD7 (ADS/0WS) DSOE (CPURDY/LMEG) DSR DSWE (PULLUP/PULLUP) DTR/CFG1 ENDIRH ENDIRL ERROR EXTSMI FRM (IRQ12/IRQ12) GND Pin No. 146 165 164 153 152 151 150 149 163 162 161 160 159 158 155 154 148 166 167 168 169 170 171 172 147 97 183 92 51 50 86 102 181 Functional Group Display interface Display interface Display interface Display interface Display interface Display interface Display interface Display interface Display interface Display interface Display interface Display interface Display interface Display interface Display interface Display interface Display interface Display interface Display interface Display interface Display interface Display interface Display interface Display interface Display interface Serial port interface Display interface Serial port interface System interface System interface Parallel port interface Power management interface Display Interface Pin State Table Number 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 5 8 5 2 2 4 6 8 10 Description Page Number 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 41 38 41 38 35 35 37 40 41 45
1, 12, 20, Power 33, 52, 53, 68, 104, 105, 121, 156, 157, 191 122 89 177 192 196 PCMCIA interface Parallel port interface Maximum ISA bus interface System interface System interface
ICDIR INIT [PCMCWE] (IOCHCHK/IOCHCHK) IOCHRDY IOCS16 [LCDDL0]
7 4 8 2 8
39 37 43 35 35
ElanTMSC300 Microcontroller Data Sheet
19
PRELIMINARY
PIN DESIGNATIONS (SORTED BY PIN NAME) (CONTINUED)
Signal Name (Alternate Functions) (IOIS16A) WP_A (IOIS16B) WP_B IOR IORESET IOW (IREQ_A) RDY_A (IREQ_B) RDY_B IRQ1 (IRQ10/PULLUP) CP2 (IRQ11/BLE) DSMD2 (IRQ12/IRQ12) FRM IRQ14 [LCDDL2] (IRQ15/IRQ15) LVEE (IRQ3/PIRQ0) PIRQ0 (IRQ4/IRQ4) M (IRQ5/PULLDN) CP1 (IRQ6/PIRQ1) PIRQ1 (IRQ7/PULLUP) DSMA1 (IRQ9/BHE) DSMD3 JTAGEN (LA17/A17) DSMA8 (LA18/A18) DSMA9 (LA19/A18) DSMA10 (LA20/A20) DSMA11 (LA21/A21) DSMA12 (LA22/A22) DSMA13 (LA23/A23) DSMA14 LCDD0 (DACK5/DACK5) LCDD1 (DRQ5/DRQ5) LCDD2 (IOCHCHK/IOCHCHK) LCDD3 (DRQ1/DRQ1) [LCDDL0] IOCS16 [LCDDL1] MCS16 [LCDDL2] IRQ14 [LCDDL3] SBHE (LDEV/RSVD) DSMD0 LF1 LF2 LF3 LF4 (LMEG/CPURDY) DSOE LPH (LRDY/DRQ6) DSMD1 Pin No. 112 118 54 140 55 111 117 195 179 167 181 198 182 194 173 178 193 164 168 199 155 154 153 152 151 150 149 144 175 177 174 196 197 198 143 148 204 205 206 207 147 190 166 Functional Group PCMCIA interface PCMCIA interface System interface Reset and power System interface PCMCIA interface PCMCIA interface System and maximum ISA bus interface Maximum ISA bus interface Maximum ISA bus interface Local and maximum ISA bus Interface System and maximum ISA bus interface Local and maximum ISA bus interface Maximum ISA bus interface Local and maximum ISA bus interface Maximum ISA bus interface Maximum ISA bus interface Maximum ISA bus interface Maximum ISA bus interface JTAG boundary scan interface Maximum ISA bus interface Maximum ISA bus interface Maximum ISA bus interface Maximum ISA bus interface Maximum ISA bus interface Maximum ISA bus interface Maximum ISA bus interface Display interface Display interface Display interface Display interface Display interface Display interface Display interface Display interface Local bus interface Miscellaneous interface Miscellaneous interface Miscellaneous interface Miscellaneous interface Maximum ISA bus interface Power management interface Local bus interface Pin State Table Number 7 7 2 9 2 7 7 2 8 8 8 8 8 2 8 8 2 8 8 9 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 9 9 9 9 8 6 8 Description Page Number 39 39 35 45 36 39 39 36, 44 44 44 44 36, 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 41 41 41 41 35 36 36 36 43 42 42 42 42 44 40 43
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
PIN DESIGNATIONS (SORTED BY PIN NAME) (CONTINUED)
Signal Name (Alternate Functions) LVDD (A12/BALE) LVEE (IRQ15/IRQ15) M (IRQ4/IRQ4) MA0/SA14 MA1/SA15 MA10/SA13 MA11/SA12 MA2/SA16 MA3/SA17 MA4/SA18 MA5/SA19 MA6/SA20 MA7/SA21 MA8/SA22 MA9/SA23 MCEH_A MCEH_B MCEL_A MCEL_B MCS16 [LCDDL1] MEMR MEMW (M/IO/DRQ3) DSMD5 MWE [PCMCOE] SLCTIN [PCMCWE] INIT PE PGP0 PGP1 PGP2 PGP3 PIRQ0 (PIRQ0/IRQ3) (PIRQ0/IRQ3) PIRQ0 PIRQ1 (PIRQ1/IRQ6) (PIRQ1/IRQ6) PIRQ1 PMC0 PMC1 PMC2 PMC3 PMC4 [PPDCS] PPDWE PPDWE [PPDCS] PPOEN Pin No. 173 182 173 24 21 10 60 19 18 17 16 15 14 13 11 130 124 129 123 197 56 57 170 8 84 89 82 189 188 187 186 194 194 193 193 137 138 77 185 184 90 90 91 Functional Group Display interface Display interface Display interface Memory bus interface Memory bus interface Memory bus interface Memory bus interface Memory bus interface Memory bus interface Memory bus interface Memory bus interface Memory bus interface Memory bus interface Memory bus interface Memory bus interface PCMCIA interface PCMCIA interface PCMCIA interface PCMCIA interface System interface System interface System interface Display interface Memory bus interface PCMCIA interface PCMCIA interface Parallel port interface Power management interface Power management interface Power management interface Power management interface System and maximum ISA bus interface System and maximum ISA bus interface System and maximum ISA bus interface System and maximum ISA bus interface Power management interface Power management interface Power management interface Power management interface Power management interface Parallel port interface Parallel port interface Parallel port interface Pin State Table Number 8 8 8 1 1 1 1 1 1 1 1 1 1 1 1 7 7 7 7 8 2 2 8 1 4 4 4 6 6 6 6 2 2 2 2 6 6 6 6 6 4 4 4 Description Page Number 41 41 42 34 34 34 34 34 34 34 34 34 34 34 34 39 39 39 39 36 36 36 41 34 38 39 37 40 40 40 40 36, 44 36, 44 36, 44 36, 44 40 40 40 40 40 37 37 37
ElanTMSC300 Microcontroller Data Sheet
21
PRELIMINARY
PIN DESIGNATIONS (SORTED BY PIN NAME) (CONTINUED)
Signal Name (Alternate Functions) RAS0 RAS1 RC RDY_A (IREQ_A) RDY_B (IREQ_B) REG_A REG_B RESIN RIN ROMCS RST_A RST_B RSTDRV RTS/CFG0 SA0 SA1 SA10 SA11 SA12 SA13/MA10 SA14/MA0 SA15/MA1 SA16/MA2 SA17/MA3 SA18/MA4 SA19/MA5 SA2 SA20/MA6 SA21/MA7 SA22/MA8 SA23/MA9 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SBHE [LCDDL3] SIN SLCT SLCTIN [PCMCOE] SOUT Pin No. 2 3 78 111 117 132 126 141 100 44 133 127 58 93 74 73 62 61 60 10 24 21 19 18 17 16 72 15 14 13 11 71 70 69 67 66 64 63 143 99 87 84 94 Functional Group Memory bus interface Memory bus interface Keyboard interface PCMCIA interface PCMCIA interface PCMCIA interface PCMCIA interface Reset and power Serial port interface Memory bus interface PCMCIA interface PCMCIA interface System interface Serial port interface System interface System interface System interface System interface System interface System interface System interface System interface System interface System interface System interface System interface System interface System interface System interface System interface System interface System interface System interface System interface System interface System interface System interface System interface System interface Serial port interface Parallel port interface Parallel port interface Serial port interface Pin State Table Number 1 1 3 7 7 7 7 9 5 1 7 7 2 5 2 2 2 2 2 1 1 1 1 1 1 1 2 1 1 1 1 2 2 2 2 2 2 2 8 5 4 4 5 Description Page Number 34 34 37 39 39 39 39 45 38 34 39 39 36 38 36 36 36 36 34 34 34 34 34 34 34 34 36 34 34 34 34 36 36 36 36 36 36 36 36 38 37 38 38
22
ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
PIN DESIGNATIONS (SORTED BY PIN NAME) (CONTINUED)
Signal Name (Alternate Functions) SPKR (SPKR_A) BVD2_A (SPKR_B) BVD2_B [SRCS0] CAS0L [SRCS1] CAS0H [SRCS2] CAS1L [SRCS3] CAS1H STRB (STSCHG_A) BVD1_A (STSCHG_B) BVD1_B SUS/RES SYSCLK [XTCLK] TC [TMS] [TCK] DACK2 [TDI] AEN [TDO] DRQ2 [TMS] TC VCC VCC1 VCC5 VMEM VPP_A VPP_B VSYS VSYS2 (W/R/DRQ7) DSMD4 WAIT_AB WP_A (IOIS16A) WP_B (IOIS16B) X1OUT [BAUD_OUT] [X14OUT] AFDT X32IN X32OUT [XTCLK] SYSCLK [XTDAT] 8042CS Pin No. 139 113 119 6 7 4 5 83 114 120 103 45 49 46 47 76 49 23, 81, 135, 180 176 95, 128 9, 22, 35 131 125 48, 65 142 169 115 112 118 200 80 201 202 45 75 Functional Group Miscellaneous interface PCMCIA interface PCMCIA interface Memory bus interface Memory bus interface Memory bus interface Memory bus interface Parallel port interface PCMCIA interface PCMCIA interface Power management interface System interface System interface JTAG boundary scan interface JTAG boundary scan interface JTAG boundary scan interface JTAG boundary scan interface Power Power Power Power PCMCIA interface PCMCIA interface Power Power Local bus interface PCMCIA interface PCMCIA interface PCMCIA interface Miscellaneous interface Miscellaneous and parallel port interface Miscellaneous interface Miscellaneous interface System and keyboard interface Keyboard interface Pin State Table Number 9 7 7 1 1 1 1 4 7 7 6 2 2 2 2 2 2 10 10 10 10 7 7 10 10 8 7 7 7 9 4 9 9 2 3 Description Page Number 36 38 38 34 34 34 34 38 38 38 40 37 37 44 44 44 44 45 45 45 45 39 39 45 45 43 39 39 39 42 37, 42 42 42 37 37
ElanTMSC300 Microcontroller Data Sheet
23
PRELIMINARY
PIN STATE TABLES
The Pin State tables beginning on page 25 are grouped by function based on their primary function when the ELANSC300 microcontroller is configured at reset for the internal LCD Controller mode (NAME1). See page 14 for a description of NAME1. The Pin State tables also show the I/O type and reset state for those pins that have been configured at reset for either Local Bus mode or Maximum ISA Bus mode. The Reset State column lists the I/O pin voltage level when all of the VCC pins are stable and the RESIN input is active. The level of the VCC pins correlating to this data is shown in Table 1.
Table 1. I/O Pin Voltage Level
Internal CGA (V) VCC AVCC VCC5 VSYS2 VSYS VMEM VCC1 3.3 3.3 5.0 3.3 5.0 3.3 3.3 Local Bus (V) 3.3 3.3 5.0 3.3 5.0 3.3 3.3 Maximum ISA (V) 3.3 3.3 5.0 5.0 5.0 3.3 3.3
Pin Characteristics
The following information clarifies the meaning of the Pin State tables beginning on page 25: The letters in the I/O Type column of Tables 1-10 mean the following: I O - Input - Output
STI - Schmitt Trigger Input B A - Bidirectional - Analog
The VCCIO column refers to the voltage supply pin on the ELANSC300 microcontroller that is directly connected to the output driver for the specified signal pin. The VCC Clamp column refers to the voltage supply pin on the ELANSC300 microcontroller that is directly connected to the ESD protection diode (cathode) for the specified signal pin. Any pin with a 5-V VCC Clamp is a "5-V safe" input. The Spec. Load (specification load) column is used to determine derated AC timing. See "Derating Curves" on page 84 of this data sheet.
The Term column refers to internal termination. The letters in this column of Tables 1-10 mean the following: PD - Pull-down resistor PU - Pull-up resistor The symbols (letters) in the Drive Type column specify the drive capability of output pins. These specifications can be found in the DC Characteristics section beginning on page 80 of this document. For a more complete description of I/O Drive Types, see "Derating Curves" on page 84 and Table 48 on page 84. The Clock Off column describes the logic level of the I/O pins while the ELANSC300 microcontroller is in any of the power management modes where the CPU clock is stopped, and power is still applied to both the VCCIO and VCC clamp supply pins associated with that I/O pin. For Doze mode, the data reflects a situation in which the internal CGA controller video refresh is disabled.
24
ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY Table 2. Memory Bus Interface
I/O Pin No. Type 2 3 4 5 6 7 10 11 13 14 15 16 17 18 19 21 24 8 44 43 O O O O O O O O O O O O O O O O O O O O Drive Type E,D,C E,D,C D D D D E,D,C E,D,C E,D,C E,D,C E,D,C E,D,C E,D,C E,D,C E,D,C E,D,C E,D,C E,D,C B B Reset State (volts) Clock Internal Local Off CGA Bus Active Active Active Active Active Active 0 0 0 0 0 0 0 0 0 0 0 1 1 1 3.3/0 3.3/0 3.3/0 3.3/0 3.3/0 3.3/0 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 5.0 5.0 3.3/0 3.3/0 3.3/0 3.3/0 3.3/0 3.3/0 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 5.0 5.0 Max ISA 3.3/0 3.3/0 3.3/0 3.3/0 3.3/0 3.3/0 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 5.0 5.0 VCCIO VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VSYS VSYS VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VCC5 VCC5 50 50 30 30 30 30 70 70 70 70 70 70 70 70 70 70 70 70 30 50 VCC Clamp Spec. Load (pF)
Signal Name
1,3
Term
RAS0
RAS1 1,3 CAS1L [SRCS2] 1,2 CAS1H [SRCS3] 1,2 CAS0L [SRCS0] 1,2 CAS0H [SRCS1] 1,2 MA10/SA13 3 MA9/SA23 3 MA8/SA22 3 MA7/SA21 3 MA6/SA20 3 MA5/SA19 3 MA4/SA18 3 MA3/SA17 3 MA2/SA16 3 MA1/SA15 3 MA0/SA14 3 MWE 3 ROMCS DOSCS
Notes: 1. These signals are active during reset. 2. These pins always default to their DRAM interface function. 3. The drive strength for these pins is programmable. E is the default. All inputs that have VCC Clamp = 5 V are 5-V safe inputs regardless of their VCCIO.
ElanTMSC300 Microcontroller Data Sheet
25
PRELIMINARY Table 3. System Interface
Signal Name Pin No. I/O Type O O O O O O O O O O O O O B B B B B B B B B B B B B B B B O(STI) I I I O(I) I(O) PD PU PU PU PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD Term Drive Type E D D D D D D D D D D D D E,D,C E,D,C E,D,C E,D,C E,D,C E,D,C E,D,C E,D,C E,D,C E,D,C E,D,C E,D,C E,D,C E,D,C E,D,C E,D,C B - -(-/-) -(-/-) B A Clock Off 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0(-) - -(-/-) -(-/-) 1 - Reset State (volts) Internal CGA 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 5.0/0 4.4 3.3 3.3 5.0 0.0 Local Bus 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 3.3 3.3 5.0/0 4.4 3.3 3.3 5.0 0.0 Max ISA 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 5.0/0 4.4 3.3 3.3 5.0 0.0 VSYS VSYS VSYS VSYS VSYS VSYS VSYS VSYS VSYS VSYS VSYS VSYS VSYS VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VSYS VCC1 VCC1 VCC1 VSYS VSYS VCCIO VCC Clamp VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VMEM VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 30 30 Spec. Load (pF) 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 30
MA11/SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 D15 2 D142 D132 D122 D112 D102 D92 D82 D72 D62 D52 D42 D32 D22 D12 D02 SYSCLK [XTCLK]1 IRQ1 PIRQ1 (PIRQ1/IRQ6) PIRQ0(PIRQ0/IRQ3) DACK2 [TCK] DRQ2 [TDO]
60 61 62 63 64 66 67 69 70 71 72 73 74 25 26 27 28 29 30 31 32 34 36 37 38 39 40 41 42 45 195 193 194 46 76
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY Table 3. System Interface (Continued)
Signal Name Pin No. I/O Type O(I) O(I) O O O O O O O O STI I [B] I [B] I [B] O [B] PU Term Drive Type B B B B B C C C C A - C C C C Clock Off 1 0 1 1 1 1 1 1 1 0 - - [0] - [0] - [0] 0[0] Reset State (volts) Internal CGA 0.0 0.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 3.3 3.3 3.3 0.0 0.0 Local Bus 0.0 0.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 3.3 3.3 3.3 0.0 0.0 Max ISA 0.0 0.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 3.3 3.3 3.3 0.0 0.0 VSYS VSYS VSYS VSYS VSYS VSYS VSYS VSYS VSYS VSYS VCC1 VCC1 VCC1 VCC1 VSYS2 VCCIO VCC Clamp VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 70 70 70 70 Spec. Load (pF) 30 30 30 30 30 50 50 50 50 30
AEN [TDI] TC [TMS] ENDIRL ENDIRH DBUFOE IOR IOW MEMR MEMW RSTDRV IOCHRDY IOCS16 [LCDDL0] MCS16 [LCDDL1] IRQ14 [LCDDL2] SBHE [LCDDL3]
47 49 50 51 59 54 55 56 57 58 192 196 197 198 143
Notes: 1. Reset State SYSCLK frequency is 4.6 MHz. 2. The drive strength for these pins is programmable. E is the default. All inputs that have VCC clamp = 5 V are 5-V safe inputs regardless of their VCCIO.
ElanTMSC300 Microcontroller Data Sheet
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PRELIMINARY Table 4.
I/O Type O(STI) I I PU PU Drive Type B - -
Keyboard Interface
Clock Off 1(-) - - Reset State (volts) Internal CGA 5.0 5.0 5.0 Local Bus 5.0 5.0 5.0 Max ISA 5.0 5.0 5.0 VCCIO VSYS VSYS VSYS VCC Clamp VCC5 VCC5 VCC5 Spec. Load (pF) 30
Signal Name 8042CS [XTDAT] RC A20GATE
Pin No. 75 78 79
Term
Notes: All inputs that have VCC clamp = 5 V are 5-V safe inputs regardless of their VCCIO.
Table 5.
I/O Type O O O O I I I I I O O
Parallel Port Interface
Drive Type D D D D - - - - - B B Clock Off Last state Last state Last state Last state - - - - - 1(1) 1(1) Reset State (volts) Internal Local CGA Bus 5.0 0.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0.0 5.0 0.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0.0 Max ISA 5.0 0.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0.0 VCCIO VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC Clamp VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 30 30 Spec. Load (pF) 100 100 100 100
Signal Name AFDT [X14OUT]1 INIT [PCMCWE]1 STRB1 SLCTIN [PCMCOE]1 ACK BUSY2 ERROR PE SLCT PPDWE [PPDCS] PPOEN
Pin No. 80 89 83 84 88 85 86 82 87 90 91
Term
Notes: 1. These outputs function as open-drain outputs in Normal Parallel Port mode, and function as CMOS drivers when the EPPMODE configuration bit is set. 2. The parallel port interface BUSY input must have an external pullup if the parallel port is to be used in EPP mode. If this pullup is not present, accesses to the parallel port in EPP mode will lock up the system. All inputs that have VCC clamp = 5 V are 5-V safe inputs regardless of their VCCIO.
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY Table 6.
I/O Type O O O I I I I I PU PU PU PU PU
Serial Port Interface
Clock Off Last state Last state Last state - - - - - Reset State (volts) Internal CGA 0.0 0.0 0.0 5.0 5.0 5.0 5.0 5.0 Local Bus 5.0 0.0 0.0 5.0 5.0 5.0 5.0 5.0 Max ISA 0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 VCCIO VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC Clamp VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 Spec. Load (pF) 50 50 50
Signal Name DTR/CFG 1 RTS/CFG0 1 SOUT CTS DCD DSR RIN SIN
Pin No. 92 93 94 96 98 97 100 99
Term
Drive Type A A A
Notes: 1. These pins are terminated externally per bus option selection. All inputs that have VCC clamp = 5 V are 5-V safe inputs regardless of their VCCIO.
Table 7.
I/O Type STI STI STI O O O O O O O B B STI STI STI STI O
Power Management Interface
Drive Type - - - B B B B B B B B B - - - - B Clock Off - - - Active Active Active Active Active Active Active Active Active - - - - Active Reset State (volts) Internal CGA 0.0 0.0 5.0 0.0 3.3 0.0 0.0 0.0 3.3 3.3 3.3 0.0 5.0 5.0 5.0 5.0 0.0 Local Bus 0.0 0.0 5.0 0.0 3.3 0.0 0.0 0.0 3.3 3.3 3.3 0.0 5.0 5.0 5.0 5.0 0.0 Max ISA 0.0 0.0 5.0 0.0 3.3 0.0 0.0 0.0 3.3 3.3 3.3 0.0 5.0 5.0 5.0 5.0 0.0 VCCIO VCC5 VCC5 VCC5 VCC1 VCC1 VSYS VCC5 VCC5 VCC1 VCC1 VCC1 VCC1 VCC5 VCC5 VCC5 VCC5 VCC1 VCC Clamp VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 50 50 50 50 50 50 50 50 50 50 Spec. Load (pF)
Signal Name ACIN EXTSMI SUS/RES PMC41 PMC31 PMC21 PMC11 PMC01 PGP3 PGP2 PGP1 PGP0 BL1 BL2 BL3 BL4 LPH
Pin No. 101 102 103 184 185 77 138 137 186 187 188 189 106 107 108 109 190
Term PD PD
Notes: 1. PMC outputs: four Low (PMC0, PMC1, PMC2, PMC4), one High (PMC3), default state after reset. All five are programmable as either active High or Low after reset. All inputs that have VCC clamp = 5 V are 5-V safe inputs regardless of their VCCIO.
ElanTMSC300 Microcontroller Data Sheet
29
PRELIMINARY Table 8.
I/O Type O O O O O STI I I STI STI I O O O O O O STI I I STI STI O O Drive Type C C B B B - - - - - - C C C A A B - - - - - B B
PCMCIA Interface
Clock Off 1 1 Active 0 3 state - - - - - - 1 1 1 Active 0 3 state - - - - - 0 0 Reset State (volts) Internal CGA 5.0 5.0 0.0 5.0 0.0 5.0 0.0 0.0 0.0 0.0 5.0 5.0 5.0 5.0 0.0 5.0 0.0 5.0 0.0 0.0 0.0 0.0 0.0 0.0 Local Bus 5.0 5.0 0.0 5.0 0.0 5.0 0.0 0.0 0.0 0.0 5.0 5.0 5.0 5.0 0.0 5.0 0.0 5.0 0.0 0.0 0.0 0.0 0.0 0.0 Max ISA 5.0 5.0 0.0 5.0 0.0 5.0 0.0 0.0 0.0 0.0 5.0 5.0 5.0 5.0 0.0 5.0 0.0 5.0 0.0 0.0 0.0 0.0 0.0 0.0 VCCIO VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC Clamp VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 50 50 50 50 50 50 50 50 Spec. Load (pF) 50 50 50 50 50
Signal Name MCEL_A MCEH_A VPP_A REG_A RST_A1 CD_A RDY_A2 WP_A2 BVD2_A2 BVD1_A2 WAIT_AB2 ICDIR MCEL_B MCEH_B VPP_B REG_B RST_B1 CD_B RDY_B2 WP_B2 BVD2_B2 BVD1_B2 CA24 CA25
Pin No. 129 130 131 132 133 110 111 112 113 114 115 122 123 124 125 126 127 116 117 118 119 120 134 136
Term
Notes: 1. External weak pull-down resistor is required. 2. The reset state of these signals will be zero only if the reset state of the PCMCIA power source is zero. All of these pins are required to be pulled up to the PCMCIA power source externally. All inputs that have VCC clamp = 5 V are 5-V safe inputs regardless of their VCCIO.
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY Table 9. Display Interface
I/O Type B (O/I) B (O/I) B (O/I) B (O/I) B (O/I) B (O/I) B (I/I) B (I/O) O O O O O O O O O O O O O O (I/I) O (0/I) O (I/I) O O Drive Type C C C C C C C C C C C C C C C C C C C E C C C B B B Reset State (volts) Clock Off 0 (1/-) 0 (LS/-) 0 (LS/-) 0 (LS/-) 0 (LS/-) 0 (LS/-) 0 (-/-) 0 (-/3 state) 0 0 0 0 0 0 0 0 (0/1) 0 (0/1) 0 (0/1) 0 (0/1) 0 0 0 (-/-) 0 (0/-) 1 (-/-) 1 1 Internal Local CGA Bus 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 0.0 3.3 5.0 0.0 3.3 3.3 0.0 0.0 0.0 0.0 0.0 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3/0 3.3 3.3 3.3 3.3 0.0 3.3 Max ISA 3.3 0.0 0.0 0.0 3.3 3.3 0.0 0.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 3.3 0.0 3.3 3.3 3.3 0.0 5.0 VCCIO VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VSYS2 VSYS2 VSYS2 VSYS2 VSYS2 VSYS2 VSYS2 VSYS2 VSYS2 VSYS2 VSYS2 VSYS2 VCC1 VCC1 VCC1 VCC1 VCC1 VSYS2 VSYS2 VCC Clamp VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 Spec. Load (pF) 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 (30) 50 50 50 30 50 30
Signal Name DSMD7 (ADS/0WS) DSMD6 (D/C/ DRQ0)1 DSMD5 (M/IO/ DRQ3)1 DSMD4 (W/R/ DRQ7)1 DSMD3 (BHE/ IRQ9)1 DSMD2 (BLE/ IRQ11)1 DSMD1 (LRDY/ DRQ6) DSMD0 (LDEV/ RSVD) DSMA14 (A23/ LA23) DSMA13 (A22/ LA22) DSMA12 (A21/ LA21) DSMA11 (A20/ LA20) DSMA10 (A19/ LA19) DSMA9 (A18/LA18) DSMA8 (A17/LA17) DSMA7 (A16/ DACK0) DSMA6 (A15/ DACK3) DSMA5 (A14/ DACK7) DSMA4 (A13/ DACK6) DSMA3 (CPUCLK/ PULLUP) 2 DSMA2 (CPURST/ RSVD) DSMA1 (PULLUP/ IRQ7) DSMA0 (NC/ PULLUP) DSWE (PULLUP/ PULLUP) DSOE (CPURDY/ LMEG) DSCE (DACK1/ DACK1)
Pin No. 172 171 170 169 168 167 166 148 149 150 151 152 153 154 155 158 159 160 161 162 163 164 165 183 147 146
Term
ElanTMSC300 Microcontroller Data Sheet
31
PRELIMINARY Table 9. Display Interface (Continued)
I/O Type O (I/I) O O (I/I) O (I/I) O (I/I) O (I/I) O (I/I) O (I/I) O (I/I) O I [B] I [B] I [B] O [B] Drive Type C C C C C C C C B E C C C C Reset State (volts) Clock Off 0 (-/-) 0 (1/1) 0 (-/-) 0 (-/-) 0 (-/-) 0 (-/-) 0 (-/-) 0 (-/-) 1 (-/-) 1(0/1) - [0] - [0] - [0] 0[0] Internal Local CGA Bus 0.0 3.3 0.0 0.0 0.0 0.0 0.0 0.0 3.3 3.3 3.3 3.3 0.0 0.0 0.0 3.3 3.3 3.3 3.3 0.0 0.0 3.3 3.3 3.3 3.3 3.3 0.0 0.0 Max ISA 0.0 5.0 0.0 3.3 3.3 3.3 3.3 3.3 3.3 5.0 3.3 3.3 0.0 0.0 VCCIO VCC1 VSYS2 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VSYS2 VCC1 VCC1 VCC1 VSYS2 VCC Clamp VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 Spec. Load (pF) 100 100 100 100 100 100 100 100 50 50 70 70 70 70
Signal Name LCDD3 (DRQ1 / DRQ1) LCDD0 (DACK5/ DACK5) LCDD1 (DRQ5/ DRQ5) LCDD2 (IOCHCHK/ IOCHCHK) M (IRQ4/IRQ4) CP1 (PULLDN/IRQ5) CP2 (PULLUP/ IRQ10) FRM (IRQ12/IRQ12) LVEE (IRQ15/ IRQ15) LVDD (A12/ BALE) IOCS16 [LCDDL0] MCS16 [LCDDL1] IRQ14 [LCDDL2] SBHE [LCDDL3]
Pin No. 174 144 175 177 173 178 179 181 182 145 196 197 198 143
Term
Notes: 1. LS in the Clock Off column stands for Last State. 2. Reset State Local Bus signal loading 920 mV-0 V. For 33-MHz operation, CPUCLK loading = 30 pF. All inputs that have VCC clamp = 5 V are 5-V safe inputs regardless of their VCCIO.
32
ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY Table 10.
I/O Type I I O A A A A O STI O I PD
Miscellaneous Interface
Clock Off - - Active - - - - (LS) 4 - (LS) 4 - Reset State (volts) Internal CGA 0.0 640 mV 1.68/0 1.52 1.48 1.52 1.68 0.0 0.0 5.0 0.0 Local Bus 0.0 920/0 1.68/0 1.52 1.48 1.52 1.68 1.24 0.0 5.0 0.0 Max ISA 0.0 920/0 1.68/0 1.52 1.48 1.52 1.68 1.24 0.0 5.0 0.0 VCCIO VCC5 AVCC AVCC AVCC AVCC AVCC AVCC VCC1 VCC VCC5 VCC1 VCC Clamp VCC5 AVCC AVCC AVCC AVCC AVCC AVCC VCC5 VCC VCC5 VCC5 50 50 Spec. Load (pF)
Signal Name IORESET 1 X32IN2 X32OUT 3 LF1 LF2 LF3 LF4 X1OUT [BAUD_OUT] RESIN SPKR4 JTAGEN
Pin No. 140 201 202 204 205 206 207 200 141 139 199
Term
Drive Type - - osc. - - - - B - B -
Notes: 1. IORESET (pin #140) requires an external pull-down resistor (~10K). 2. Reset State Local Bus signal and Reset State ISA Max signal: 920 mV-0 V frequency = 32 kHz. 3. Reset State signal: 1.68 V-0 V frequency = 32 kHz. 4. LS in the Clock Off column stands for Last State. All inputs that have VCC clamp = 5 V are 5-V safe inputs regardless of their VCCIO.
Table 11. Power Pins
I/O Drive Clock Type Term Type Off Reset State (volts) Internal CGA 3.3 3.3 5.0 3.3 5.0 3.3 3.3 Local Bus 3.3 3.3 5.0 3.3 5.0 3.3 3.3 Max ISA 3.3 3.3 5.0 5.0 5.0 3.3 3.3 VCCIO VCC Clamp Spec. Load (pF)
Signal Name AVCC1 VCC1 VCC51 VSYS21 VSYS1 VMEM1 VCC11 GND 203
Pin No.
23, 81, 135,180 95, 128 142 48, 65 9, 22, 35 176 1,12, 20, 33, 52, 53, 68, 104, 105, 121, 156, 157, 191 208
AGND
Notes: 1. These reset state entries identify the VCCIO levels that are present on the ELANSC300 microcontroller for the three bus mode options. Note that the device is not limited to these VCC levels. All inputs that have VCC clamp = 5 V are 5-V safe inputs regardless of their VCCIO.
ElanTMSC300 Microcontroller Data Sheet
33
PRELIMINARY
PIN DESCRIPTIONS
Descriptions of the ELANSC300 microcontroller pins are organized into the following functional groupings: n Memory bus interface n System interface n Keyboard interface n Parallel port interface n Serial port interface
n PCMCIA interface n Power management interface n Display interface n Miscellaneous interface n Local bus interface n Maximum ISA bus interface n JTAG boundary scan interface n Reset and power
MEMORY BUS INTERFACE
CAS1H [SRCS3], CAS1L [SRCS2], CAS0H [SRCS1], CAS0L [SRCS0] n For cycles that are not targeted to system memory or internal I/O, MA11-MA0 are used to provide nonmultiplexed ISA-type address signals SA23-SA12, as shown in Table 12. See also SA11-SA0 on page 36.
Column Address Strobe (Outputs; Active Low)
Column Address Strobe indicates to DRAM that a valid column address is present on the MA10-MA0 lines. Two CAS signals are allocated to each 16-bit bank, one per byte. When SRAM, instead of DRAM, is configured as main memory, SRCS3, SRCS2, SRCS1, and SRCS0 are the alternate pin functions corresponding to CAS1H, CAS1L, CAS0H, and CAS0L respectively. Each pin selects a byte in one of two possible 16-bit-wide SRAM banks. The SRAM functionality is selected via firmware. In this mode, all four of these outputs are active Low. For more information about SRCS3-SRCS0, see page 49. DOSCS
Table 12.
MA 11 10 SA
Non-Multiplexed Address Signals Provided by MA11-MA0
9 8 7 6 5 4 3 2 1 0
12 13 23 22 21 20 19 18 17 16 15 14
MWE
Write Enable (Output; Active Low)
Write Enable is the write command strobe for the DRAM and SRAM devices. RAS1-RAS0
DOS ROM Chip Select (Output; Active Low)
The DOS ROM Chip Select is an active Low output that provides the chip select function for the Flash/ROM array banks that are used to hold the operating system or application code. DOSCS is used to select the DOS ROMs and can be configured to respond to direct addressing or Memory Management System (MMS) addressing. MA11-MA0/SA23-SA12
Row Address Strobe (Output; Active Low)
Row Address Strobe indicates to DRAM that a valid row address is present on the MA11-MA0 lines. One RAS signal is allocated for each 16-bit DRAM bank, one per word. ROMCS
BIOS ROM Chip Select (Output; Active Low)
BIOS ROM Chip Select is an active Low output that provides the chip select function for the Flash/ROM array. ROMCS is used to select the BIOS ROM, and can be configured to respond to direct addressing or MMS addressing. When configured for direct addressing, the BIOS ROM can reside at one or all of the following address ranges: 0F0000h-0FFFFFh 0E0000h-0EFFFFh 0D0000h-0DFFFFh 0C0000h-0CFFFFh 0A0000h-0AFFFFh The BIOS ROM chip select is also active for accesses into the 64-Kbyte segment that contains the boot vector, at address FF0000h to FFFFFFh.
Memory Address (Outputs; Active High)
Memory address lines for multiplexed and nonmultiplexed memory devices; their effect depends on the system configuration and the type of bus cycle. n When system memory is configured as DRAM, the MA10-MA0 signals are multiplexed outputs and convey the row address during RAS assertion and column address during CAS assertion. n When system memory is configured as SRAM, MA11-MA0 output the system addresses, SA12- SA23, and are used in conjunction with SA1-SA11.
34
ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY For more information about the ROMCS pin, see the Using 16-Bit ROMCS Designs in Elan TM SC300 and ElanSC310 Microcontrollers Application Note, order #21825. This is a dual-function pin. When the JTAGEN signal is asserted, it will function as the TDO, JTAG Test Data Out pin. See "JTAG Boundary Scan Interface" on page 44 for more information on the function of this pin during Test mode. ENDIRH
SYSTEM INTERFACE
AEN [TDI]
High Byte Data Buffer Direction Control (Output; Active High)
This output controls the transceiver on the high byte of the data bus, bits 15-8. When asserted, this signal is used to enable the data from the ELANSC300 microcontroller data bus to the buffered data bus. ENDIRL
DMA Address Enable (Output; Active High)
AEN is used to indicate that the current address active on the SA23-SA0 address bus is a memory address and that the current cycle is a DMA cycle. All I/O devices should use this signal in decoding their I/O addresses and should not respond when this signal is asserted. When AEN is asserted, the DACKx signals are used to select the appropriate I/O device for the DMA transfer. This is a dual-function pin. When the JTAGEN signal is asserted, it functions as the TDI, JTAG Test Data Input pin. D15-D0
Low Byte Data Buffer Direction Control (Output; Active High)
This output controls the transceiver on the low byte of the data bus, bits 7-0. When asserted, this signal is used to enable the data from the ELANSC300 microcontroller data bus to the buffered data bus. IOCHRDY
System Data Bus (Bidirectional; Active High)
The System Data Bus inputs data during memory and I/O read cycles, and outputs data during memory and I/O write cycles. During Local Bus and DRAM/SRAM cycles, this bus represents the CPU data bus. DACK2 [TCK]
I/O Channel Ready (Input; Active High)
This signal is used by ISA slave devices to add wait states to the current transfer. When this signal is deasserted, wait states are added. IOCS16 [LCDDL0]
(Input; Active Low)
This input is used to signal to the ISA control logic that the targeted I/O device is a 16-bit device. (IOCS16 is available unless the internal LCD Controller Bus mode is selected and a dual-scan LCD panel interface is selected via firmware.)
IOCS16 is generated by a 16-bit ISA I/O expansion board when the board recognizes it is being addressed. IOCS16 provides the same function for 16-bit I/O expansion devices as the MCS16 signal provides for the 16-bit memory devices.
DMA Channel 2 Acknowledge (Output; Active Low)
This output indicates that the current transfer is a DMA transfer to the I/O device connected to this DMA channel. In PC-compatible system designs, this signal can be connected to the floppy disk controller DMA acknowledge input. This is a dual-function pin. When the JTAGEN signal is asserted, it functions as the TCK (JTAG Test Clock) pin. See "JTAG Boundary Scan Interface" on page 44 for more information on the function of this pin during Test mode. DBUFOE
Note: IOCS16 is internally OR'd with MCS16. Do not tie IOCS16 Low.
For more information about the IOCS16 pin, see the Using 16-Bit ROMCS Designs in ElanTM SC300 and ElanSC310 Microcontrollers Application Note, order #21825. IOR
Data Buffer Output Enable (Output; Active Low)
This output is used to control the output enable on the system data bus buffer. When Low, the outputs of the Data Bus Buffer are enabled. DRQ2 [TDO]
DMA Channel 2 Request (Input; Active High with Internal Pulldown)
This input is used to request a DMA transfer. It can be connected to the floppy disk controller DMA request output in PC-compatible system designs.
I/O Read Command (Output; Active Low)
The IOR signal indicates that the current cycle is a read of the currently selected I/O device. When this signal is asserted, the selected I/O device can drive data onto the data bus.
ElanTMSC300 Microcontroller Data Sheet
35
PRELIMINARY IOW PIRQ0 (PIRQ0/IRQ3), PIRQ1 (PIRQ1/IRQ6)
I/O Write Command (Output; Active Low)
The IOW signal indicates that the current cycle is a write of the currently selected I/O device. When this signal is asserted, the selected I/O device can latch data from the data bus. IRQ1, IRQ14 [LCDDL2]
Programmable Interrupt Requests (Inputs; Rising Edge/Active High, with Internal Pullup)
These two inputs can be programmed to drive any of the available interrupt controller interrupt request inputs. For more information, see the PIRQ Configuration Register, Index B2h, in the Elan TM SC300 Microcontroller Programmer's Reference Manual, order #18470. RSTDRV
Interrupt Request Channels 1 and 14 (Input; Rising Edge/Active High, with Internal Pullup)
This input is connected to the internal 8259A-compatible Interrupt Controller Channels 1 and 14. In PC-compatible systems, IRQ1 may be connected to the 8042 keyboard controller. (IRQ14 is available unless the internal LCD Controller Bus mode is selected and a dual-scan panel interface is selected via firmware.) MCS16 [LCDDL1]
System Reset (Output; Active High)
This signal is the ISA-compatible reset signal. When this signal is asserted, all connected devices reinitialize to their reset state. The pulse width of RSTDRV is adjustable, based on PLL startup timing. For more information, see "Loop Filters" on page 97 and the powerup sequence timings beginning on page 99. SA11-SA0
(Input; Active Low)
This input is used to signal to the ISA control logic that the targeted memory device is a 16-bit device. (MCS16 is available unless the internal LCD Controller Bus mode is selected and a dual-scan LCD panel interface is selected via firmware.)
MCS16 is generated by a 16-bit memory expansion card when the card recognizes it is being addressed. This signal tells the data bus steering logic that the addressed memory device is capable of communicating over both data paths. When accessing an 8-bit memory device, the MCS16 line remains deasserted, indicating to the data bus steering logic that the currently addressed device is an 8-bit memory device capable of communicating only over the lower data path.
System Address Bus (Output; Active High)
The system address bus outputs the physical memory or I/O port, least-significant, latched addresses. They are used by all external I/O devices and all memory devices other than main system DRAM. During main system SRAM and local bus cycles, this bus represents the CPU address bus (A11-A1). SA0 is equivalent to A0 during local bus cycles. See MA11-MA0 on page 34 for SA23-SA12. SBHE [LCDDL3]
(Output; Active Low)
Active when the high byte is to be transferred on the upper 8 bits of the data bus. (SBHE is available unless the internal LCD Controller Bus mode is selected and a dual-scan LCD panel interface is selected via firmware.) SPKR
Note: MCS16 is internally ORed with IOCS16. Do not tie MCS16 Low.
For more information about the MCS16 pin, see the Using 16-Bit ROMCS Designs in Elan TM SC300 and ElanSC310 Microcontrollers Application Note, order #21825. MEMR
Speaker, Digital Audio Output (Output)
This signal controls an external speaker driver. It is generated from the internal 8254-compatible Timer Channel 2 output ANDed with I/O port 061h, bit 1 (speaker data enable).
Memory Read Command (Output; Active Low)
The MEMR signal indicates that the current cycle is a read of the currently selected memory device. When this signal is asserted, the selected memory device can drive data onto the data bus. MEMW
Memory Write Command (Output; Active Low)
The MEMW signal indicates that the current cycle is a write of the currently selected memory device. When this signal is asserted, the selected memory device can latch data from the data bus.
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY TC [TMS]
PARALLEL PORT INTERFACE
ACK
Terminal Count (Output; Active High)
This signal is used to indicate that the transfer count for the currently active DMA channel has reached zero, and that the current DMA cycle is the last transfer. This is a dual-function pin. When the JTAGEN signal is asserted, it will function as the TMS, JTAG Test Mode Select pin. See the "JTAG Boundary Scan Interface" on page 44 for more information on the function of this pin during Test mode.
Printer Acknowledge (Input; Active Low)
The printer asserts ACK to confirm that the transfer from the ELANSC300 microcontroller to the parallel port was successful. AFDT [X14OUT]
Auto Line Feed Detect (Output; Active Low)
This pin signals the printer to autofeed continuous form paper. It can be programmed to become a 14.336-MHz output. BUSY
KEYBOARD INTERFACE
8042CS [XTDAT]
Printer Busy (Input; Active High)
The printer asserts BUSY when it is performing an operation. ERROR
Keyboard Controller Chip Select (Output; Active Low)
This signal is a decode of A9-A0 = 060h to 06Eh, all even addresses. In PC-compatible systems, it connects to the external keyboard controller chip select. XTDAT is the PC/XT keyboard data line. A20GATE
(Input; Active Low)
The printer asserts the ERROR signal to inform the parallel port of a deselect condition, PE, or other error condition. INIT [PCMCWE]
Address Bit-20 Gate (Input; Active High)
When deasserted, this signal is used to force CPU address bit 20 Low, a function required for PC compatibility. In PC-compatible systems, this signal can be driven by an 8042 keyboard controller, port 2, bit 1. For detailed information about the A20GATE signal, see the ElanTMSC300 and ElanSC310 Microcontrollers GATEA20 Function Clarification Application Note, order #21811. RC
Initialize Printer (Output; Active Low)
This pin signals the printer to begin an initialization routine. It can be programmed to become the PCMCIA write enable signal (PCMCWE). PE
Paper End (Input; Active High)
The printer asserts this signal when it is out of paper. PPDWE [PPDCS]
Reset CPU (Input; Active Low)
This signal resets the internal CPU. In PC-compatible systems, this signal can be driven by a keyboard controller, port 2, bit 0. SYSCLK [XTCLK]
Parallel Port Write Enable (Output; Active Low)
The PPDWE signal is used to control the 374 type latch in a unidirectional parallel port design. To support a bidirectional parallel port design, this pin can be reconfigured (PPDCS) to act as an address decode for the parallel port data port. It can then be externally gated with IOR and IOW to provide the Parallel Port Data Read and Write Strobes, respectively. For more information, see "Parallel Port" on page 61. PPOEN
System Clock (Output)
This clock can be used to provide a clock to a keyboard controller. It is not synchronous to ISA bus cycles. XTCLK is the PC/XT keyboard clock. For information about internal clock states, see Table 23 on page 54. For information about the maximum ISA bus option, see page 65.
Parallel Port Output Buffer Enable (Output; Active Low)
This signal supports a bidirectional parallel port design. It is used to control the output enable of the Parallel Port Output Buffer. SLCT
Printer Select Return (Input; Active High)
The printer asserts SLCT when it has been selected.
ElanTMSC300 Microcontroller Data Sheet
37
PRELIMINARY SLCTIN [PCMCOE] The state of this signal is used to determine the pin configuration at power-up. For more information, see "Alternate Pin Functions" on page 68. SIN
Printer Selected (Output; Active Low)
Asserting SLCTIN selects the line printer. This pin can be programmed to become the PCMCIA output enable signal (PCMCOE). For more information, see "Parallel Port" on page 61. STRB
Serial Data In (Input; Active High)
This signal is used to receive the serial data from the external serial device into the internal serial port controller. SOUT
Strobe (Output; Active Low)
Asserting STRB signals the line printer to latch data currently on the parallel port.
Serial Data Out (Output; Active High)
This signal is used to transmit the serial data from the internal serial port controller to the external serial device.
SERIAL PORT INTERFACE
CTS
Clear To Send (Input; Active Low)
This signal indicates that the external serial device is ready to accept data. DCD
PCMCIA INTERFACE
BVD1_A (STSCHG_A), BVD1_B (STSCHG_B)
Battery Voltage Detect (Inputs)
These signals are generated by the memory card as an indication of the condition of its battery for a memory card interface. For an I/O card interface, these inputs are the card's Status Change Interrupt (active Low). BVD2_A (SPKR_A), BVD2_B (SPKR_B)
Data Carrier Detect (Input; Active Low)
This signal indicates to the internal serial port controller that the attached serial device has detected a data carrier. DSR
Data Set Ready (Input; Active Low)
This signal is used to indicate that the external serial device is ready to establish a communication link with the internal serial port controller. DTR/CFG1
Battery Voltage Detect (Inputs)
These signals are generated by the memory card as an indication of the condition of its battery for a memory card interface. For an I/O card interface, these pins become the speaker inputs from the cards. CA24
Data Terminal Ready (Output; Active Low)
This signal indicates to the external serial device that the internal serial port controller is ready to communicate. The state of this signal is used to determine the pin configuration at power-up. For more information, see "Alternate Pin Functions" on page 68. RIN
Card Address Bit 24 (Output)
This card address bit is controlled by accessing the ELANSC300 microcontroller configuration registers and should be connected to the card interface signal A24. This address signal is common to slot A and slot B interfaces. CA25
Card Address Bit 25 (Output)
This card address bit is controlled by accessing the ELANSC300 microcontroller configuration registers, and should be connected to the card interface signal A25. This address signal is common to slot A and slot B interfaces. CD_A, CD_B
Ring Indicate (Input; Active Low)
This signal is used as a modem control function. A change in state on this signal by the external serial device causes a modem status interrupt. This signal can be used to cause the ELANSC300 microcontroller to resume from a suspended state. RTS/CFG0
Card Detect (Inputs; Active Low)
The card detect signals indicate that the card is properly inserted into a socket. These signals should be driven from an "ANDing" of the CD1 and CD2 pins of a single socket. Therefore, two external AND gates are required, one for each slot.
Request To Send (Output; Active Low)
This signal indicates to the external serial device that the internal serial port controller is ready to send data.
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY ICDIR RST_A, RST_B
Card Data Direction (Output)
This signal controls the direction of the card data buffers or translators, working in conjunction with the MCEL_x and MCEH_x card enable signals to control the data buffers on the card interface. When this signal is High, the data flow is from the ELANSC300 microcontroller to the card socket, indicating a data write cycle. When this signal is Low, the data flow is from the card socket into the ELANSC300 microcontroller, indicating a read cycle. Note that PCMCIA bus buffering may or may not be implemented in a system design. MCEH_A, MCEH_B
Card Reset (Outputs; Active High)
These signals reset their respective cards. When active, this signal clears the Card Configuration Option register, thus placing a card in a memory-only mode. VPP_A, VPP_B
Program and Peripheral Voltage Control (Output; Active High)
These signals can be used to enable the programming voltages to their respective card interfaces. WAIT_AB
Extend Bus Cycle (Input; Active Low)
This signal delays the completion of the memory access or I/O access that is currently in progress. When this signal is asserted (Low), wait states will be inserted into the cycle in progress. A two-card solution needs each slot's WAIT_AB signal "ANDed" before being input to the ELANSC300 microcontroller. WP_A (IOIS16A), WP_B (IOIS16B)
Card Enables, High Byte (Output; Active Low)
These signals enable odd address bytes for their respective card interfaces. MCEL_A, MCEL_B
Card Enables, Low Byte (Output; Active Low)
These signals enable even address bytes for their respective card interfaces. PCMCOE
Write Protect (Inputs; Active High)
When a memory interface is selected, this signal indicates the status of the targeted device's Write Protect Switch. When the targeted device is configured for an I/O interface, the WP_A signal is used to indicate that the currently accessed port is a 16-bit port (IOIS16x active Low). Both WP_A and WP_B signals indicate that the targeted device is a 16-bit device during I/O access to the targeted device. When the targeted device is configured as an I/O access, the two signals are OR'd together to generate the IOIS16x signal. When the targeted device is configured as an I/O access, there is basically no difference between the WP_A and WP_B signals.
Card Memory Output Enable (Output, Active Low)
The Parallel Port SLCTIN signal can be programmed to become PCMCOE. PCMCOE indicates that a memory read cycle from the card interface is being performed. PCMCWE
Card Memory Write Enable (Output, Active Low)
The Parallel Port INIT signal can be programmed to become PCMCWE. PCMCWE indicates that a memory write cycle to the card interface is being performed. RDY_A (IREQ_A), RDY_B (IREQ_B)
Card Ready (Inputs; Active High)
This signal indicates that the respective card is ready to accept a new data transfer command if a memory interface is selected. If the card interface is configured as an I/O interface, the Socket A I/O card's IREQ_A signal uses RDY_A as a general purpose input pin that may be used as the card interrupt request input into the ELANSC300 microcontroller (active High). For more information about socket A card's IREQ_A signal, see Chapter 5 in the Elan TM SC300 Microcontroller Programmer's Reference Manual, order #18470. REG_A, REG_B
Attribute Memory Select (Output; Active Low)
This signal selects either the Attribute Memory or the Common Memory. This signal will be inactive (High) for accesses to Common Memory, and asserted (Low) for accesses to Attribute Memory. This signal is also asserted (Low) for all I/O accesses.
ElanTMSC300 Microcontroller Data Sheet
39
PRELIMINARY
POWER MANAGEMENT INTERFACE
ACIN
AC Input Status (Input; Active High)
When asserted, this signal disables all power management functions (if so enabled). It can be used to indicate when the system is being supplied power from an AC source. BL4-BL1
register bit if configured to do so. PGP2 and PGP3 can also be configured for a specific state when the PMU is in the off state. PGP2 and PGP3 can be programmed to be set to a pre-defined state for Micro Power Off mode. For more information about PGP3-PGP0, see the ElanTM SC300 Microcontroller Programmer's Reference Manual, order #18470B and Using 10-Bit ROMCS Designs in ElanTMSC300 and ElanSC310 Microcontrollers Application Note, order #21825. PMC4-PMC0
Battery Low Detects (Inputs; Negative Edge Sensitive)
These signals are used to indicate to the ELANSC300 microcontroller the current status of the battery. BL4- BL1 can indicate various conditions of the battery as status changes. A High indicates normal operating conditions, while a Low indicates a low voltage warning condition. These inputs can be used to force the system into one of the power saving modes when activated, as follows: n BL1 can be programmed to force the system to go to Low Speed PLL mode or to generate an SMI. n BL2 can be programmed to force the system to enter Sleep mode if not already in Sleep mode, or to generate an SMI. n BL3 can only be programmed to generate an SMI. n BL4 can be programmed to force the system to enter Suspend mode. EXTSMI
Power Management Controls (Output; Programmable)
Power Management Control outputs control the power to various external devices and system components. The PMC0, PMC1, PMC2, and PMC4 signals are asserted Low immediately after reset, and the PMC3 signal is asserted High immediately after reset. Each of the PMC pins can then be programmed to be High or Low for each of the ELANSC300 microcontroller power management modes. SUS/RES
Suspend/Resume Operation (Input; Rising Edge)
When the ELANSC300 microcontroller is in High Speed PLL, Low Speed PLL, or Doze mode, a positive edge on this pin causes the internal logic to step down through the Power Management modes (one per refresh cycle) until Sleep mode is entered. If in Sleep, Suspend, or Off mode, a positive edge on this pin causes the ELANSC300 microcontroller to enter the High Speed PLL mode.
External System Management Interrupt (Input; Edge Sensitive)
This input is provided to allow external logic to generate an SMI request to the CPU. It is edge triggered, with the polarity programmable. LPH
Latched Power Control (Output; Active Low)
This signal is the inverse of BL4 if ACIN is not true and BL4 is enabled. PGP3-PGP0
DISPLAY INTERFACE
The signals listed as part of the display interface are only available when the ELANSC300 microcontroller is configured with the internal LCD controller enabled. If the internal LCD controller is disabled, the functions of these pins change to support either a CPU local bus interface or maximum ISA bus interface. The pins required for physical connection to the microcontroller are listed at the end of this section on page 42. For more information about the LCD controller, see the Configuring the ElanTMSC300 Device's Internal CGA Controller for a Specific LCD Panel Application Note, order #20749.
Programmable Chip Select Generation (Input/Output)
PGP0 and PGP1 can be programmed as input or output. The default is input. PGP2 and PGP3 are output only. These general purpose pins can be individually programmed as decoder outputs or chip selects for other external peripheral devices. PGP0 and PGP2 can be gated with I/O write or act as an address decode only. PGP1 and PGP3 can be gated with I/O Read or act as an address decode only. PGP0 and PGP1 can be directly controlled via a single
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY CP1 LCDD1
LCD Panel Line Clock (Output)
This is the Line Clock when in internal LCD mode and an LCD configuration is selected. It is activated at the start of every pixel line refresh cycle. CP1 should be connected to the equivalent line on the LCD panel. CP2
LCD Data Bit (Output)
When in internal LCD mode and an LCD configuration is selected, this signal is data bit 1. LCDD1 should be connected to the corresponding pin on the LCD panel. LCDD2
LCD Data Bit (Output)
When in internal LCD mode and an LCD configuration is selected, this signal is data bit 2. LCDD2 should be connected to the corresponding pin on the LCD panel. LCDD3
LCD Panel Shift Clock (Output)
This is the nibble/byte strobe when in internal LCD mode and an LCD configuration is selected. CP2 is also known as the shift clock or data shift. It is used by the LCD to latch data. CP2 should be connected to the equivalent line on the LCD panel. DSCE
LCD Data Bit (Output)
When in internal LCD mode and an LCD configuration is selected, this signal is data bit 3. LCDD3 is the MSB and should be connected to the corresponding MSB pin on the LCD panel. [LCDDL3-LCDDL0]
Display SRAM Chip Enable (Output; Active Low)
This signal generates the external video SRAM Chip Enable. DSMA14-DSMA0
Display SRAM Address Bus (Output)
These signals generate the address to the SRAM. Up to 32 Kbyte can be supported for the display interface. DSMD7-DSMD0
LCD Panel Data Bits for Dual-Scan Panels (Outputs)
When the ELANSC300 microcontroller is programmed to support LCD Dual-Scan Panel mode (separate data bits for the top and bottom half of the panel), these bits (LCDDL3-LCDDL0) are for the bottom half of the screen. LCDD3-LCDD0 are the data bits for the top half of the screen. LCD Dual-Scan Panel mode is selected via firmware. LCDDL0 is the LSB for the lower panel and LCDDL3 is the MSB for the lower panel. These pins are shared with IOCS16, MCS16, IRQ14, and SBHE (described in "System Interface", beginning on page 35.) LCDDL3-LCDDL0 should be connected to their corresponding pins on the dual-screen LCD lower panel. LVDD
Display SRAM Data Bus (Bidirectional)
These signals provide the data bus used for the video SRAM. DSOE
Display SRAM Output Enable (Output; Active Low)
This signal controls the video SRAM Output Enable pin. DSWE
Display SRAM Write Enable (Output; Active Low)
When asserted, this signal indicates a Write to the video SRAM. FRM
LCD Panel VDD Voltage Control (Output; Active Low)
This signal is used to control the assertion of the LCD's VDD driver. LVDD is provided to be part of the solution in sequencing the panel's VDD, DATA, and VEE signals in the proper order. LVEE
LCD Panel Line Frame Start (Output)
This signal is asserted at the start of every frame (panel scan) when in LCD mode and an LCD configuration is selected. FRM is also known as FLM or frame. It should be connected to the equivalent line on the LCD panel. LCDD0
LCD Panel VEE Voltage Control (Output; Active Low)
This signal is used to control the assertion of the LCD's VEE driver. LVEE is provided to be part of the solution in sequencing the panel's VDD, DATA, and VEE signals in the proper order.
LCD Data Bit (Output)
When in internal LCD mode and an LCD configuration is selected, this signal is data bit 0. LCDD0 is the LSB and should be connected to the corresponding LSB pin on the LCD panel.
ElanTMSC300 Microcontroller Data Sheet
41
PRELIMINARY M [X14OUT]
LCD Panel AC Modulation (Output)
In internal LCD mode, this is the AC modulation signal for the LCD. AC modulation causes the LCD to change polarity on its crystal material to keep the LCD from forming a DC bias. Some LCD panels do not require this signal. Connect M to the equivalent line on the LCD panel if appropriate. LCD Physical Pin Connections To connect an LCD panel to the ELANSC300 microcontroller, the following pins need to be connected: n CP1 n CP2 n FRM n LCDD3-LCDD0 n LCDDL3-LCDDL0 (dual-scan panel only) nM The other connections that are required vary. For example: n Contrast voltage can be positive or negative, typically about -22 V. n +5 V n GND n Display enable usually requires a simple 5-V enable signal that some panels require. This can easily be connected to one of the ELANSC300 microcontroller's PMC pins. n VEE is typically a voltage in the same range as the contrast voltage. Refer to the panel specifications for more information.
14-MHz Output
The Parallel Port AFDT output can be programmed to become X14OUT, a 14.336-MHz clock. X32IN, X32OUT
32.768-kHz Crystal Interface
These pins are used for the 32.768-kHz crystal. This is the main clock source for the ELANSC300 microcontroller and is used to drive the internal Phase-Locked Loops that generate all other clock frequencies needed in the system. For more information, see "Crystal Specifications" on page 95.
LOCAL BUS INTERFACE
The local bus interface pins are only available when the ELANSC300 microcontroller's internal LCD controller is disabled and the ELANSC300 microcontroller pin configuration is set to support a CPU local bus and a partial ISA bus. The following list of pins is specific to local bus functionality. In Local Bus mode, additional ISA pins are also available. These pins are described in the next section "Maximum ISA Bus Interface" because these pins are available in both Local Bus and Maximum ISA Bus modes. For more information, see "CPU Local Bus Interface versus Internal LCD Interface" on page 69 and Tables 37- on page 73. A23-A12
Local Bus Upper Address Lines (Output) These signals are the local bus CPU address lines when in Local Bus mode. These signals are combined with the SA11-SA0 signals to form the complete CPU address bus during local bus cycles.
ADS
MISCELLANEOUS INTERFACE
LF1, LF2, LF3, LF4 (Analog inputs)
Local Bus Address Strobe (Output; Active Low)
Local Bus Address Strobe is an active Low address strobe signal for 386 local bus devices. BHE
Loop Filters
These pins are used to connect external components that make up the loop filters for the internal PLLs. For more information, see "Loop Filters" on page 97. X1OUT [BAUD_OUT]
Local Bus Byte High Enable (Output; Active Low)
This signal indicates to the local bus devices that data is being transferred on the high byte of the data bus. BLE
14-MHz/UART Output
This can be programmed to be either the 14.336-MHz clock or the serial baud rate clock for serial infrared devices. The 14.336-MHz output can be used by external video controllers. As BAUD_OUT, it is 16 x the bit data rate of the serial port and is used by serial infrared devices.
Local Bus Byte Low Enable (Output; Active Low)
This signal indicates to the local bus devices that data is being transferred on the low byte of the data bus.
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY CPUCLK
MAXIMUM ISA BUS INTERFACE
The pins listed below as part of the "ISA Bus Interface" are only available when the ELANSC300 microcontroller pin configuration is configured to enable the maximum ISA Bus. When the maximum ISA bus interface is enabled, the internal LCD controller and the CPU local bus interface are disabled. (This mode does not support master and ISA refresh cycles.) For more information, see "Maximum ISA Interface versus Internal LCD Interface" on page 70, Table 37-Table on page 73, and the ElanTMSC300 and ElanTMSC310 Devices' ISA Bus Anomalies Application Note, order #20747. 0WS
CPU 2X Clock (Output)
This is the timing reference for the local bus device. The high-speed PLL can be programmed to provide one of the clock frequencies shown on page 53. CPURDY
386 CPU Ready Signal (Output; Active Low)
This signal shows the current state of the 386 core CPU's CPURDY signal. CPURST
CPU Reset (Output; Active High)
This signal is used to force the local bus device to an initial condition. It is also used to allow the local bus device to synchronize to the CPUCLK. This signal is taken directly from the internal CPU reset. D/C
Local Bus Data/Control (Output; Active Low)
This signal indicates to the local bus devices that the current cycle is either a Data cycle or a Control cycle. A Low on this signal indicates that the current cycle is a Control cycle. LDEV
Zero Wait State (Input; Active Low) This input can be driven active by an ISA memory device to indicate that it can accept a Zero Wait State memory cycle.
BALE
Bus Address Latch Enable (Output; Active High) This PC/AT-compatible signal is used by external devices to latch the LA signals for the current cycle.
DACK7, DACK6, DACK5, DACK3, DACK2, DACK1, DACK0
Local Bus Device Select (Input; Active Low)
This signal is used by the local bus devices to signal that they will respond to the current cycle. If LDEV is not driven active by the time specified in Table 57 on page 108, then the cycle defaults to an ISA bus cycle. LRDY
DMA Acknowledge (Output; Active Low) DMA acknowledge signals are active Low output pins that acknowledge their corresponding DMA requests. Note: The DACK2 signal is available regardless of the ELANSC300 microcontroller's bus mode. DACK1 and DACK5 are also available in the local bus pin configuration.
DRQ7, DRQ6, DRQ5, DRQ3, DRQ2, DRQ1, DRQ0
Local Bus Device Ready (Input; Active Low) This signal is used by the local bus devices to terminate the current bus cycle.
M/IO
DMA Request (Input; Active High)
DMA Request signals are asynchronous DMA channel request inputs used by peripheral devices to gain access to a DMA service.
Local Bus Memory/I/O (Output; Active Low) This signal indicates to the local bus devices that the current cycle is either a memory or an I/O cycle. A Low on this signal indicates that the current cycle is an I/O cycle.
W/R
Note: The DRQ2 signal is available regardless of the ELANSC300 microcontroller's bus mode. DRQ1 and DRQ5 are also available in the local bus pin configuration.
IOCHCHK
Local Bus Write/Read (Output; Active Low) This signal indicates to the local bus devices that the current cycle is either a Read or a Write cycle. A Low on this signal indicates that the current cycle is a Read cycle.
I/O Channel Check (Input; Active Low)
This is a PC/AT-compatible signal used to generate an NMI or SMI.
Note: IOCHCHK is also available in the Local Bus pin configuration.
ElanTMSC300 Microcontroller Data Sheet
43
PRELIMINARY IRQ15, IRQ14, IRQ12-IRQ9, IRQ7-IRQ3, IRQ1 The JTAG pins described here are shared pin functions. They are enabled by the JTAGEN signal. JTAGEN
Interrupt Request (Inputs; Rising Edge/Active High Trigger)
Interrupt Request input pins signal the internal 8259 compatible interrupt controller that an I/O device needs servicing. IRQ3 and IRQ6 are shared with PIRQ0 and PIRQ1. IRQ0 is internally connected to the counter/timer, and IRQ8 is internally connected to the real-time clock. IRQ2 is used for cascading, and IRQ13 is reserved. IRQ0, IRQ2, IRQ8, and IRQ13 are not available externally.
JTAG Enable (Input; Active High)
This pin enables the JTAG pin functions. When it is High, the JTAG interface is enabled. When it is Low, the JTAG pin functions are disabled and the pins are configured to their default functions. See the Pin Designations, System Interface, and Miscellaneous Interface tables for the JTAG pin default function descriptions. For more information, see "System Test and Debug" on page 74. [TCK]
Note: IRQ4, IRQ12, and IRQ15 are also available in the Local Bus pin configuration.
LA23-LA17
Test Clock (Input)
Test clock is a JTAG input clock that is used to access the test access port when JTAGEN is active. [TDI]
Latchable ISA Address Bus (Outputs)
These are the ISA latchable address signals. These signals are valid early in the bus cycle so that external peripherals may have time to decode the address and return certain control feedback signals such as MCS16. LMEG
Test Data Input (Input)
Test data Input is the serial input stream for JTAG scan input data when JTAGEN is active. [TDO]
Address is in Low Meg (Output; Active Low)
This signal is active (Low) whenever the address for the current cycle is in the first Mbyte of memory address space (SA23 = SA22 = SA21 = SA20 = 0).
Test Data Output (3-State Output)
Test data Output is the serial output stream for JTAG scan result data when JTAGEN is active. [TMS]
Note: LMEG should not be used to generate SMEMR or SMEMW. Instead, address lines SA23-SA20 should be decoded. For more information about LMEG, see the Elan TM SC300 and Elan TM SC310 Devices' ISA Bus Anomalies Application Note, order #20747.
Test Mode Select (Input)
Test Mode Select is an input for controlling the Test Access Port when JTAGEN is active.
RESET AND POWER JTAG BOUNDARY SCAN INTERFACE
The ELANSC300 microcontroller provides an IEEE Std 1149.1-1990 (JTAG) compliant Standard Test Access Port (TAP) and Boundary-Scan Architecture. The boundary-scan test logic consists of a boundary scan register and support logic that are accessed through the TAP. The TAP provides a simple serial interface that makes it possible to test the microcontroller and system hardware in a production environment. The TAP contains extensions that allow a hardwaredevelopment system to control and observe the microcontroller without interposing hardware between the microcontroller and the system. The TAP can be controlled via a bus master. The bus master can be either automatic test equipment or a component (PLD) that interfaces to the four-pin test bus. See the Voltage Partitioning section on page 95 for more information about power. AGND
Analog Ground pin
This pin is the ground for the analog circuitry and is broken out separately from the other GND pins making it possible to filter AGND in a system that has a lot of noise on the ground plane. In most applications, AGND is tied directly to the ground plane with the other ground pins on the microcontroller. AVCC
3.3 V (only) Supply Pin
This supply pin provides power to the analog section of the ELANSC300 microcontroller's internal PLLs. Extreme care should be taken that this supply voltage is isolated properly to provide a clean, noise-free voltage to the PLLs
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY AVCC is required for battery backup. For more information about battery backup, see the ElanTMSC300 and ElanTMSC310 Microcontrollers Solution For Systems Using a Back-Up Battery Application Note, order #20746. GND VMEM
3.3-V or 5-V Supply Pins
These supply pins provide power to the Memory Interface and Data Bus pins (D15-D0). These pins must be connected to the same DC supply as the system DRAMs. VSYS
System Ground Pins
These pins provide electric grounding to all non-analog sections of the ELANSC300 microcontroller's internal CPU and peripherals. IORESET
3.3 V or 5 V Supply Pins
These supply pins provide power to a subset of the ISA address and command signal pins, in addition to external memory chip selects, buffer direction controls, and other miscellaneous functions. VSYS2
Reset Input (Input; Active Low)
IORESET is an asynchronous hardware reset input equivalent to POWERGOOD in the PC/AT system architecture. Asserting this signal does not reset the RTC RAM invalid bit. Asserting IORESET without asserting RESIN causes the ELANSC300 microcontroller to go into Micro Power Off mode. For more information, see "Micro Power Off Mode" on page 55. RESIN
3.3 V or 5 V Supply Pins These supply pins provide power to some of the ELANSC300 microcontroller alternate system interface pins.
FUNCTIONAL DESCRIPTION
The ELANSC300 microcontroller architecture consists of several components, as shown in the device block diagram. These components can be grouped into eight main functional modules: 1. The Am386SXLV microprocessor core itself, including System Management Mode (SMM) power management hardware 2. A memory controller and associated mapping hardware 3. Two PCMCIA Revision 2.1 slots 4. An additional power management controller that interfaces to the CPU's System Management Mode (SMM) and is integrated tightly with internal clock generator hardware 5. Core peripheral controllers (DMA, interrupt controller, and timer) 6. Additional peripheral controllers (UART, parallel port, and real-time clock) 7. PC/AT support features 8. An integrated LCD controller, optional local bus controller, or optional maximum ISA bus The remainder of this section describes these modules.
Master Reset (Input; Active Low)
RESIN indicates that main power is being applied to the ELANSC300 microcontroller for the first time. When this signal is asserted, the RTC and internal registers are reset. The RESIN signal supersedes the IORESET signal. VCC
3.3 V (only) DC Supply Pins
These supply pins provide power to the ELANSC300 microcontroller core. Refer to AC Characteristics for VCC power up timing restrictions. The VCC pins are required for battery backup. For more information about battery backup, see the ElanTMSC300 and ElanTMSC310 Microcontrollers Solution For Systems Using a Back-Up Battery Application Note, order #20746. VCC1
3.3 V or 5 V Supply Pin
This supply pin provides power to a subset of the LCD/ alternate, power management, and ISA interface pins. VCC5
5 V DC Supply Pins
These supply pins provide power to the 5 V only interface pins. These pins could be 3.3 V in a pure 3.3-V system.
Am386SXLV CPU Core
The CPU core component is a full implementation of the AMD Am386SXLV 32-bit, low-voltage microprocessor (with I/O pads removed). For more information about the Am386 microprocessors, see the
ElanTMSC300 Microcontroller Data Sheet
45
PRELIMINARY
Am386(R)SX/SXL/SXLV Data Sheet, order #21020 and the Am386(R)DX/DXL Data Sheet, order #21017.
Along with standard 386 architectural features, the CPU core includes SMM. SMM and the other features of the CPU are described in the Am386DXLV and Am386SXLV Microprocessors Technical Reference Manual, order #16944.
banks supporting up to 16 Mbyte of DRAM, utilizing industry standard modules. The ELANSC300 microcontroller shares the DRAM address lines MA0-MA11 with the upper system address lines SA12-SA23 to reduce pin count. This signal sharing is shown in Table 14.
Memory Controller
The ELANSC300 microcontroller memory controller is a unified control unit that supports a high-performance, 16-bit data path to DRAM or SRAM. No external memory bus buffers are required and up to 16 Mbyte in two 16-bit banks can be supported. System memory must always be configured as 16-bits wide. For more information about the memory controller, see Chapter 2 of the ElanTMSC300 Microcontroller Programmer's Reference Manual, order #18470. The System Block Diagram, Figure 7 on page 64 of this manual, shows a typical palm-top memory configuration. The ELANSC300 microcontroller's memory controller supports an EMS-compatible Memory Mapping System (MMS) with 12 page registers. This facility can be used to provide access to ROM-based software. MMS is also used in the PCMCIA slot support. Shadow RAM is also supported. The Memory Controller supports one of three different memory operating modes: SRAM, Page mode DRAM, or Enhanced Page mode DRAM. Enhanced Page mode increases DRAM access performance by effectively doubling the DRAM page size in a two-bank DRAM system by arranging the address lines such that one page is spread across both DRAM banks. Both DRAM modes use standard Fast Page mode DRAMs. The memory controller operation is synchronous with respect to the CPU. This ensures maximum performance for all transfers to local memory. The clock stretching implemented by the clock generation circuitry works to reduce synchronous logic power consumption. As shown in Table 13, the two DRAM operating modes are defined by the MOD field in the Memory Configuration Register, Index 66h, bit 0.
Table 14.
MA and SA Signal Pin Sharing
DRAM Memory Address MA9-MA0 MA10 MA11
System Address SA23-SA14 SA13 SA12
The ELANSC300 microcontroller also shares the DRAM data bus with the system data bus on the D15-D0 pins. In a typical system, an SD bus is created with an external x 16 bit buffer or level translator to isolate the DRAM data bus from the rest of the system. Refer to the Typical System Block Diagram, Figure 7 on page 64 of this data sheet. The DRAM configurations are supported as shown in Table 11. The bank size information in the table also applies when system memory is configured as SRAM; however, SRAM uses a different addressing scheme than DRAM and shares the same address lines as the ISA bus. Chapter 2 in the ElanTM SC300 Microcontroller Programmer's Reference Manual, order #18470, contains more information. Note that the configurations that use 512 Kbyte x 8 bit and 1 Mbyte x 16 bit DRAMs employ asymmetrical addressing. Table 16 and Table 17 show the relationship of the CPU address mapped to the DRAM memory.
Table 13.
0 1
DRAM Mode Selection
Function Page mode Enhanced Page mode
MOD0 (Index 66h, bit 0)
The ELANSC300 microcontroller defaults to a DRAM interface. The SRAM mode is selected via bit 0 of the Miscellaneous 6 Register Index 70h. The memory controller provides for a direct connection of two 16-bit
46
ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY Table 15. Supported DRAM/SRAM Configuration
Bank Size (16-Bit Wide Only) Total DRAM/SRAM Size 512 Kbyte 512 Kbyte 1 Mbyte 1 Mbyte 1 Mbyte 2
1
Index B1h Bit 7 0 0 0 0 x x x 1 x 1 x x Bit 6 0 0 1 1 x x x 0 x 1 x x
Index B4h Bit 7 1 1 1 1 0 0 0 1 0 1 0 0
Index Reg. 66h MS2 Bit 4 x x x x 0 0 0 x 1 x 1 1 MS1 Bit 3 x x x x 0 1 1 x 0 x 0 1 MS0 Bit 2 x x x x 1 0 1 x 0 x 1 0
Bank 0 DRAMs 4 256 K x 4 bits 1 256K x 16 bits 4 256 K x 4 bits 1 256K x 16 bits 2 512 K x 8 bits 2 512 K x 8 bits 4 1 Mbyte x 4 bits 1 1 Mbyte x 16 bits 4 1 Mbyte x 4 bits, 1 1 Mbyte x 16 bits 4 4 Mbyte x 4 bits 4 4 Mbyte x 4 bits
Bank 1 DRAMs -- -- 4 256 K x 4 bits 1 256K x 4 bits -- 2 512 K x 8 bits -- -- 4 1 Mbyte x 4 bits 1 1 Mbyte x 16 bits -- 4 4 Mbyte x 4 bits
Mbyte1
2 Mbyte1 2 Mbyte 4 Mbyte1 4 Mbyte 8 Mbyte1 16 Mbyte1
Notes: 1. SRAM configuration is supported. Bit 7 of the PCMCIA Card Reset Register, Index B4h, must be cleared. Setting MS2-MS0 of Index 66h as specified in the table selects the SRAM bank sizes. See Tables 16 and 17 for the DRAM address multiplexing schemes for normal page mode and Enhanced Page mode, respectively.
ElanTMSC300 Microcontroller Data Sheet
47
PRELIMINARY
Table 16.
Index B4h Index 66h Index B1h DRAM
DRAM Address Translation (Page Mode)
DRAM Address
Bit 7 0 0 0 0 0 0 1 1 1
Bits 432 0 0 11 0 1 01 011 100 101 110 xxx xxx x x x1
Bits 76 xx xx xx xx xx xx 00 01 10
Size Bank 0 Bank 1 RAS MA11MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 (Byte) (Byte) (Byte) CAS 1M 2M 2M 4M 8M 16M 512K 1M 2M 1M 1M 2M 2M 8M 8M 512K 512K 2M - 1M - 2M - 8M - RAS CAS RAS CAS RAS CAS RAS CAS RAS CAS RAS CAS RAS CAS - - - - - - - - - - - - - - - - - - - - - - - - A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 - A9 A8 A7 A6 A5 A4 A3 A2 A1 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 - A9 A8 A7 A6 A5 A4 A3 A2 A1 A19 A18 A17 A16 A15 A14 A13 A12 A11 A20 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A19 A18 A17 A16 A15 A14 A13 A12 A11 A20 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1
A22 A19 A18 A17 A16 A15 A14 A13 A12 A21 A20 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A22 A19 A18 A17 A16 A15 A14 A13 A12 A21 A20 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 - - - - A9 - - - - - A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1
512K RAS CAS -
RAS A20 CAS -
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 - - A8 A7 A6 A5 A4 A3 A2 A1
Notes: 1. Asymmetrical addressing applies to configurations using DRAM with 512K x 8 and 1M x 16 organizations. Page mode DRAM using two banks of 1 Mbyte x 16 DRAMs is not supported. Use Enhanced Page mode for two-bank configuration. See Table 17 for the supported Enhanced Page mode configurations. See Table 15 for the physical organization of the DRAM devices supported. Bit 0 of the Memory Configuration 1 Register, Index 66h, must be cleared for normal (non-enhanced) page mode.
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY Table 17.
Index Index Index B4h 66h B1h Bit 7 0 0 0 1 1 Bits 432 0 1 01 100 110 xxx x x x2 Bits 76 xx xx xx 01 11
DRAM Address Translation (Enhanced Page Mode)
DRAM Address
DRAM
Size Bank 0 Bank 1 RAS MA11MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 (Byte) (Byte) (Byte) CAS 2M 4M 16M 1M 4M 1M 2M 8M 512K 2M 1M 2M 8M RAS CAS RAS CAS RAS CAS - - - - - - - - - - - - A19 A18 A17 A16 A15 A14 A13 A12 A11 A20 - A9 A8 A7 A6 A5 A4 A3 A2 A1 A19 A18 A17 A16 A15 A14 A13 A12 A21 A20 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1
A22 A19 A18 A17 A16 A15 A14 A13 A23 A21 A20 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 - - - - A18 A17 A16 A15 A14 A13 A12 A11 A19 A9 A8 A7 A6 A5 A4 A3 A2 A1
512K RAS CAS 2M
RAS A20 CAS -
A21 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 - - - A8 A7 A6 A5 A4 A3 A2 A1
Notes: 1. Bit 4 of the Version Register, Index 64h must also be set for 2-Mbyte Enhanced Page mode. Also, bit 0 of Memory Configuration 1 Register, Index 66h, must be a 1. 2. When 16-Mbit asymmetric DRAMs are used in a two-bank configuration (4 Mbyte), bits 1 and 0 of the Memory Configuration 1 Register, Index 66h, must be set for Enhanced Page mode only. See Table 11 for a description of the physical organization of the DRAM devices supported. Bit 0 of the Memory Configuration 1 Register, Index 66h must be set to enable Enhanced Page mode. Bit 1 of the Memory Configuration 1 Register, Index 66h, must be set for DRAM. If set for SRAM, bits 0 and 1 control wait states.
SRAM
When using SRAM instead of DRAM for main memory, up to 16 Mbyte can be accessed, the SRAM being organized as one or two banks. Each bank is 16 bits wide and is provided with a low and high byte select. An SRAM memory interface is selected by setting bit 0 of the Miscellaneous 6 Register, Index 70h. If this is done, CAS1H, CAS1L, CAS0H, and CAS0L will have their alternate function as SRAM chip select pins 3-0 (SRCS3-SRCS0). Table 18 shows the key SRAM access pins. The MS2-MS0 bits in the Memory Configuration Register, Index 66, are also used to program the total SRAM size. Bit 7 of the PCMCIA Card Reset Register, Index B4h, must be cleared for SRAM configurations. Table 19 contains information about SRAM wait state logic, and Table 30 on page 71 contains SRAM interface alternate pin information.
Table 18. SRAM Access Pins
Pin Name SRCS0 SRCS1 SRCS2 SRCS3 SA23-SA1 MWE I/O O O O O O O Function SRAM Bank 0 Low Byte Select SRAM Bank 0 High Byte Select SRAM Bank 1 Low Byte Select SRAM Bank 1 High Byte Select Address (16 Mbyte maximum) Write enable
See Table 15 on page 47 for bank size settings.
ElanTMSC300 Microcontroller Data Sheet
49
PRELIMINARY Table 19.
Configuration Index 63h Bit 4 x 0 1 Index 66h Bits 1 and 0 00 01 01
SRAM Wait State Select Logic
Number of Wait States Read 0 1 2 Write 1 1 2 SRAM Speed 20 MHz 45 ns 80 ns 120 ns 25 MHz 35 ns 55 ns 100 ns 33 MHz 25 ns 35 ns 70 ns
Notes:
Refer to Index 70h, bit 0, in the ElanTMSC300 Microcontroller Programmer's Reference Manual, order #18470 for information on how to select SRAM versus DRAM.
PCMCIA Slots
Th e Ela nSC300 m ic roc ontr oll er s uppor ts two revision 2.1 PCMCIA slots. MMS mapping logic is used to access the PCMCIA memory address space. Up to twelve 16-Kbyte pages of the CPU's address space are mapped into windows of PCMCIA memory address space. Depending on the system requirements, the address and data lines to the PCMCIA slots may or may not require external buffers (see Figure 7 on page 64). For more information, see Chapter 2 in the ElanTMSC300 Microcontroller Programmer's Reference Manual, order #18470. Also see the Elan T M SC300 and ElanSC310 Microcontrollers Memory Management Application Note, order #21823 and the Using a PCMCIA Card as a Boot ROM on an ElanTMSC300 Microcontroller Design Application Note, order #21824. 4. Sleep. Additional clocks and peripherals are stopped after additional inactivity has been detected. The exact parameters can be programmed. The Low-Speed PLL can be left on, so a quick startup is possible. 5. Suspend. Virtually all of the system is shut down, including all clocks, the 8254 timer, and the Phase Locked Loops (a programmable recovery time is associated with this mode). The 32.768-kHz clock input is still running. 6. Off. This level is virtually the same as Suspend mode. Two outputs can be programmed to change state when the transition from Suspend mode to Off mode occurs. DRAM refresh can be disabled in OFF mode. In addition, the ELANSC300 microcontroller can manage the power consumption of peripheral devices. This control can be forced upon entering a specific operating mode or it can be handled directly by firmware. The ELANSC300 microcontroller PMU controls five power management control (PMC) pins that are controlled by the operating modes. Clock Generation The ELANSC300 microcontroller requires only one 32.768-kHz clock input that is used to generate all other clock frequencies required by the system. This 32.768-kHz clock input is provided through the X32IN and X32OUT pins and the crystal oscillator circuit. This input frequency is then used to internally drive multiple Phase-Locked Loops that create all necessary frequencies. The clock rate that is used to drive the internal CPU is determined by the mode of operation of the ELANSC300 microcontroller. The clock generation, control, and distribution scheme are detailed in Figure 1 and Figure 2, which follow.
The PMU Modes and Clock Generators
The Power Management Unit (PMU) monitors all system activities (e.g., keyboard, screen, and disk events), and, based on the state of the system, determines in which operating mode the system should be running. The PMU supports six operating modes, each defined by a different combination of CPU and peripheral operation, as shown in the list that follows. 1. High-Speed PLL. All clocks are at their fastest speed and all peripherals are powered up. This is the mode the system enters when activity is detected by the PMU. 2. Low-Speed PLL. The internal CPU clock is reduced to a maximum of 4.608 MHz. All other clocks and peripherals operate at full speed. This is the first level of power conservation; it is entered after a specified elapsed time with no activity. 3. Doze. The second level of power conservation. The CPU, system, and DMA clocks are stopped. The high-speed PLL is turned off. This mode is entered after a specified elapsed time with no activity.
50
ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
Programmable 32 kHz Input INT_PLL
EN
1.4746 MHz
EN
LS_PLL
HS_PLL
EN
2 x CPU Clock
1.1892 MHz 1.8432 MHz 18.432 MHz
36.864 MHz
/2
2.048 MHz LS_PLL_EN VID_PLL HS_PLL_EN
EN
14.336 MHz
VID_PLL_EN
Figure 1.
PLL Block Diagram
ElanTMSC300 Microcontroller Data Sheet
51
PRELIMINARY
(ISA Cycle) + (DMA Cycle) + (Low Speed)
2 x CPU Clock 0 2 x CPU/Local Bus Clock
High Speed PLL (I4)
1
/2 18.432 9.216 18.432 MHz Divide Chain 4.608 2.304 1.152 I4 I3 I2 I1 I0 S[1:0] Programmable Low Speed (I0-I3) (Low-Speed PLL mode only) /2 S2 /4
Internal SYSCLK DMA Clock
External SYSCLK
Figure 2.
Clock Steering Block Diagram
52
ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY In the PLL Block Diagram, the INT_PLL is the Intermediate PLL, and is used to multiply the 32.768-kHz input frequency by 45 to produce a 1.4746-MHz input for use by the LS_PLL and the VID_PLL. The LS_PLL, or LowSpeed PLL, is used to again multiply the 1.4746-MHz input by 25 to produce a 36.864-MHz output. This output of the LS_PLL is then divided down to provide the frequencies shown in Table 21. The LS_PLL also generates a 2.048-MHz signal used by the VID_PLL or Video PLL to generate the 14.336-MHz clock used by the Internal LCD Controller. This frequency is also available on the X1OUT pin for use by an external video controller if selected. The HS_PLL can be programmed to provide one of the high-speed CPU clock frequencies shown in Table 20. During operation in Low-Speed PLL mode, the CPU clock is driven from Low-Speed clock output of the Low-Speed PLL divide chain. The CPU clock frequency used during Low Speed mode is programmable to the following frequencies: 4.608 MHz, 2.304 MHz, 1.152 MHz, and 0.567 MHz. During Doze, Sleep, and Suspend modes of operation, the CPU clock is normally stopped. This clock operates at 9.216 MHz when it is running. Slow-refresh and self-refresh DRAMs are supported by the ELANSC300 microcontroller. The refresh timer source and the refresh rate are selectable. When the CPU clock is stopped, the only clock source for refresh is the 32-kHz clock. CAS-before-RAS DRAM refresh is performed. When the DMA subsystem is idle, the DMA clock control logic stops the clock input to the DMA controllers. The DMA clock is started whenever any of the DREQ inputs go High. When the DMA cycle is in progress, the DMA clock remains active as long as a DREQ input is High or the internal AEN signal is active. To reduce power consumption in Doze, Sleep, and Suspend modes, the CPU clock is turned off. To further reduce the power consumption in these three modes, the High-Speed PLL is shut off. The Low-Speed PLL is left on by default, but can be programmed to turn off in all three modes. For information about the signals associated with power management (ACIN, BL4-BL1, EXTSMI, LPH, PGP3-PGP0, PMC4-PMC0, and SUS/RES), see "Power Management Interface" on page 40. For more information, see Chapter 1 of the ElanTMSC300 Microcontroller Programmer's Reference Manual, order #18470.
Table 20.
High-Speed CPU Clock Frequencies
HS_PLL Output Frequency 39.496 MHz 50.023 MHz 65.829 MHz
2 x CPU Frequency 40 MHz 50 MHz 66 MHz
ELANSC300 Microcontroller Power Management
Dynamic CPU clock switching is the primary form of power management in the ELANSC300 microcontroller. When the system is in the High-Speed PLL mode, the ELANSC300 microcontroller can be configured to use the High-Speed clock output of the PLL for main memory, local bus accesses, CPU idle cycles, and ROM accesses configured to use the High-Speed clock. During cycles to I/O devices, PCMCIA, ROM, and other external ISA devices, the CPU clock is dynamically switched to the output of the Low-Speed PLL.
Table 21.
Phase-Locked Loops INT_PLL LS_PLL Frequency 1.4746 MHz 36.864 MHz 1.8432 MHz 1.1892 MHz HS_PLL VID_PLL 39.496 MHz, 50.023 MHz, or 65.829 MHz 14.336 MHz
PLL Output
Where Used LS_PLL and VID_PLL Divide by 2 16450 UART clock 8254 Timer clock Input to high speed/low speed MUX LCD Controller
ElanTMSC300 Microcontroller Data Sheet
53
PRELIMINARY Table 22.
Mode Power On High-Speed PLL Low-Speed PLL Doze Sleep Suspend Off
PMU Modes
Description
After Power-on reset, system enters High-Speed PLL mode. The system will be in this mode as long as activities are detected by activity monitor (described in the Programmable Activity Mask Registers, Indexes 08h, 75h, and 76h). The system will enter this mode from High-Speed PLL mode after a programmable 1/512 s to 1/2 s, or 1/16 s to 16 s of inactivity. The system will enter this mode from Low-Speed PLL mode after a programmable 1/16 s to 16 s, or 1/2 s to 128 s of inactivity. The system will enter this mode from Doze mode after a programmable 4 s to 17 minutes of inactivity. The system will enter this mode from Sleep mode after a programmable 1/16 s to 16 s of inactivity. The system will enter this mode from Suspend mode after a programmable 1 to 256 minutes of inactivity.
Table 23.
Mode High-Speed PLL Low-Speed PLL Doze Sleep Suspend Off High-Speed CPU CLK 33/25/20 MHz Low-Speed CPU CLK 9.2 MHz
Internal Clock States
VIDEO CLK 14.336 MHz DMA CLK 4.6 MHz 2.3/1.2/ 0.58/0.29 MHz DC1 SYSCLK 9.2 MHz 9.2 MHz 8254 CLK (Timer) 1.19 MHz 1.19 MHz 16450 CLK (UART) 1.8432 MHz 1.8432 MHz
4.608/2.304/ 4.608/2.304/ 14.336 MHz 1.152/0.567 MHz 1.152/0.567 MHz DC1 DC DC DC DC1 9.2 MHz/DC4 9.2 MHz/DC4 9.2 MHz/DC4 14.3 MHz/DC2
9.2 MHz/DC2 1.19 MHz/DC2 1.8 MHz/DC2 DC DC DC 1.19 MHz/DC2 1.8 MHz/DC2 1.19 MHz/DC2 1.8 MHz/DC2 1.19 MHz/DC3 1.8 MHz/DC3
14.3 MHz/DC2 4.6 MHz/DC4 14.3 MHz/DC2 4.6 MHz/DC4 14.3 MHz/DC3 4.6 MHz/DC4
Notes: All power management features will be disabled when AC power is detected via the ACIN pin being High. A register is provided to implement "software ACIN" by writing 1 to bit 5 in the Miscellaneous 6 Register, Index 70h. The DMA clock can be stopped except during DMA transfers. The Function Enable Register, Index B0h, controls this function. The CPU clock speed in Low-Speed PLL mode is selectable, (see the PMU Control 3 Register, Index ADh). The CPU Clock speed: 1. Can be programmed to run intermittently (on IRQ0) at 9.2 MHz. 2. Programmable option (but not on per-clock basis; i.e., all clocks with this note are controlled by a single ON/OFF select for that PMU mode). 3. Programmable option, will reflect setting in Suspend mode. 4. Can be programmed to run at 9.2 MHz during temporary-on NMI/SMI handlers.
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY PMC and PGP Pins The ELANSC300 microcontroller supports five power management control (PMC) pins and four programmable general purpose (PGP) pins. The PMC pins can be used to control the VCC rails of peripheral devices. The PMC pins are related to the operating modes of the ELANSC300 microcontroller PMU. The PGP pins can be used as general I/O chip selects for various uses. The PMC4-PMC0 pins are controlled by Configuration Registers at Indexes 80h, 81h, ABh, and ACh. Each pin can be programmed to be activated upon entry into any of the PMU modes or driven directly by software. PMC0 can be activated when the system is in HighSpeed PLL or Low-Speed PLL modes; PMC1 when the system is in Doze mode; PMC2 when the system is in Sleep mode; PMC3 and PMC4 when the system is in Suspend mode; or just about any other combination. These pins can then be used by the system designer to shut off power to particular peripherals when the system enters certain modes, just as internal clocks are slowed or stopped in these modes. Upon the rising edge of RESIN, PMC0, PMC1, PMC2, and PMC4 are asserted Low and PMC3 is asserted High. Prior to this edge, these signals are undefined. The ELANSC300 microcontroller can be programmed to reset a timer when an I/O access to a preset address range is detected. If no I/O activity in that range occurs before the timer expires, the ELANSC300 microcontroller can assert a PMC signal to turn off the device. When S/W accesses that address range later, the ELANSC300 microprocessor can generate a System Management Interrupt (SMI) to the processor, which then activates an SMI handler routine. This routine then can determine the cause of the SMI and take appropriate action, such as powering the I/O device back on. The PGP3-PGP0 pins are controlled by several configuration registers (70h, 74h, 89h, 91h, 94h, 95h, 9Ch, A3h, and A4h) and their behavior is very flexible. PGP0 and PGP1 can be programmed as input or output. PGP2 and PGP3 are dedicated outputs. PGP1 and PGP3 can be gated with I/O reads, PGP0 and PGP2 can be gated with I/O writes, or each can act as an address decode for a chip select. The following paragraphs describe the ELANSC300 microcontroller in Micro Power Off mode. The following are distinctive characteristics: n Minimum Power Consumption mode (approximately 25 A typical, AVCC, and Core VCC combined; AVCC and VCC are mandatory for Micro Power Off mode). n Allows the system designer to utilize the internal RTC and RTC RAM to maintain time, date, and system configuration data while the other system peripherals are powered off. n Provides the system designer with the option of keeping the system DRAM powered and refreshed while other system peripherals are powered off. Self-refresh and CAS-before-RAS refresh DRAMs are supported. n Minimal external logic required to properly control power supplies and/or power switching. n No external buffering required to properly power down system hardware. The ELANSC300 microcontroller allows a system designer to easily maintain the internal RTC and RTC RAM and optionally, the DRAM interface, while the rest of the system peripherals attached directly to the device are powered off. All ELANSC300 microcontroller power pins associated with the I/O pins of external powered-off peripherals must be powered down also. This, in addition to internal termination, provides the required isolation to allow the external peripherals to be powered off. Automatically controlled internal I/O termination is provided to terminate the internal nodes of the ELANSC300 microcontroller properly when required. The DRAM CAS-before-RAS, or self-refresh, can be maintained by the ELANSC300 microcontroller in this Micro Power State, if configured to do so, utilizing the 32-kHz oscillator. This clock continues to drive the RTC and a portion of the core logic. See the ElanTMSC300 and ElanTMSC310 Microcontrollers Solution For Systems Using a Back-up Battery Application Note, order #20746 for more information about the 32-kHz oscillator and the RTC. The VMEM power plane (DRAM/ SRAM section power) must remain powered on if the CAS-before-RAS refresh option is selected while in the Micro Power state. The VMEM power plane must also remain powered on if the self-refresh option is selected and the specific DRAM device requires any of its control pins (i.e., WE, CAS, RAS, etc.) to remain inactive in the Self-Refresh mode. If this is not required, it may be possible for the system designer to remove power from the VMEM pins when entering the Micro Power state, even when the Self-Refresh mode DRAMs remain powered on.
Micro Power Off Mode
Micro Power Off mode is the power management mode that is used for battery backup. Micro Power Off mode allows the system designer to remove power from the VCC1, VSYS, VSYS2, VCC5, and optionally, VMEM power inputs to the microcontroller. This allows the RTC timer and RAM contents to be kept valid by using a battery back-up power source on the VCC core and AVCC pins, which typically should use only 25 A in this mode.
ElanTMSC300 Microcontroller Data Sheet
55
PRELIMINARY
Power Supply Swapping Circuit
AVCC
Analog Secondary Power Supply ISA/LOCAL/LCD ISA/ L O C A L / L C D P C M C I A
On/Off
R
RESIN C M E M O R Y
RTC PMU
+ -
VCC (Core)
ELANSC300 Microcontroller
3.3 V
IORESET 5V
Primary Power Supply
Main Battery
ISA and Misc.
Parallel/Serial Power Management
ACIN
Figure 3. Typical System Design with Secondary Power Supply to Maintain RTC When Primary Power Supply is Off (DRAM Refresh is Optional.) A portion of a typical system using a secondary power supply to maintain the RTC and RTC RAM (and optionally system DRAM) is shown in Figure 3. This secondary power supply could be as simple as a small lithium coin cell battery as indicated in the diagram, but is certainly not limited to this. Note that when all primary power supply outputs are turned off, all of the system's peripherals are powered off (DRAM optional), all of the ELANSC300 microcontroller's power planes are powered off except AVCC (analog) and VCC (core), and the secondary power supply is "switched in" to maintain the ELANSC300 microcontroller's core and analog power source. For more information about back-up batteries, see the ElanTMSC300 and ElanTMSC310 Microcontrollers Solution For Systems Using a Back-up Battery Application Note, order #20746. The RESIN pin acts as the master reset. When active, all of the internal registers and components are reset, including the RTC, and the RTC RAM invalid bit will be set. This causes an issue with the power-loss bit (VRT), Index 0Dh, bit 7 of the RTC map. The VRT bit is intended to provide a method of determining when the RTC core voltage supply has dropped below an acceptable level. On a 146818A-compatible device, anything below 2.4 V will cause a low-battery condition and will cause the power-loss bit to go Low. On the ELANSC300 microcontroller, the 32-KHz clock used by RTC to maintain time stops oscillating before the VRT bit or RAM con56 tents get cleared because the VRT bit will only get cleared when the RESIN pin is asserted Low. Thus, the RTC time will be inaccurate even though the RAM contents are valid and the VRT bit is still set.
Note: Although the 32-KHz clock stops oscillating before the power-loss bit is cleared, this event occurs well before the 2.4-V specification for proper ELANSC300 microcontroller functionality. The RESIN pin should only be asserted (pulsed) Low when a power source is initially applied to the device's core and analog sections. For more information about these notes, see the ElanTMSC300 and ElanTMSC310 Microcontrollers Solution For Systems Using a Back-up Battery Application Note, order #20746.
The IORESET signal is intended to be the normal "POWER GOOD" status from the primary power supply in the example design shown in Figure 3. The IORESET input does not reset the RTC and will not set the RTC RAM invalid bit. IORESET (when the inactive state is detected) will cause the ELANSC300 microcontroller to go through its power-up sequence including PLL start-up for clock generation and an internal CPU reset. See Figure 32 through Figure 35, beginning page 100, for the initial power-up timing requirements and for Micro Power mode exit timing.
ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY When entering Micro Power Off mode and the primary power supply outputs are turned off, all of the ELANSC300 microcontroller's powered-down I/O pins are essentially tri-stated and the internal pull-ups are removed because the VCCIO and VCC CLAMP of the output driver have been removed, as shown in Figure 34 on page 101. This provides the ability to power off external peripherals that are attached directly to the ELANSC300 microcontroller without concern of driving current into the pins of the external powered-down device. To assure that the ELANSC300 microcontroller does not draw excessive power while in this state, internal pulldown resistors will be enabled. Enabling these resistors keeps the input buffers from floating (see Figure 4). The ELANSC300 microcontroller samples the two reset inputs (RESIN and IORESET) to logically determine what state the power pins are in; and, in turn, controls the internal pull-down resistors. Note that in Micro Power Off mode, the IORESET input should be terminated with a pull-down resistor if not driven Low by an external device (see Table 24 on page 59 for information about internal I/O pull-down states). Micro Power Off DRAM Refresh Refresh can be either enabled or disabled during Micro Power Off mode, and the VMEM power can be optionally removed, provided that either the memory is also powered off or all DRAM interface signals are kept at 0 V. See the timing diagrams in Figure 34 and Figure 35 on page 101 for more information. The system designer has the option to keep the system DRAM powered up and refreshed while the ELANSC300 microcontroller is in the micro power state. A configuration bit, the Micro Power Refresh Enabled bit, exists in the PMU section of the core logic to realize this feature. This is bit 2 of the Miscellaneous 3 Register at Index BAh. If this bit is cleared (default), the core logic associated with the DRAM refresh will be disabled when the ELANSC300 microcontroller is in the Micro Power state. If the bit is set, the core logic associated with the DRAM refresh will be enabled and functional while the ELANSC300 microcontroller is in its Micro Power state.
Core Logic
I/O Driver VCCIO VCC CLAMP
Pins
Pull-Up Resistor Data Out To Core Logic VCC Core Output Enable Level Translator and Pre-Driver
IN BUF
I/O PAD
Level Translator and Pre-Driver
Force Term Pull-Down Resistor
Where: VCCIO = VCC5, VMEM, VSYS, VSYS2, AVCC, or VCC1 VCC CLAMP = VCC5, VMEM, or AVCC Figure 4. ELANSC300 Microcontroller I/O Structure
ElanTMSC300 Microcontroller Data Sheet
57
PRELIMINARY The type of Micro Power DRAM refresh performed (CAS-before-RAS refresh, or self refresh) will be the same as that for which the part was configured before the IORESET pin sampled Low. If the micro power refresh feature is enabled for CAS-before-RAS refresh, the system designer should maintain power on the VMEM power pin of the ELANSC300 microcontroller and not remove power from the DRAM devices. If the micro power refresh feature is enabled for self refresh, the system designer may or may not be required to maintain power on the VMEM power pin of the ELANSC300 microcontroller, depending on the specific requirement of the DRAM device in Self-Refresh mode. Power should not be removed from the DRAM device itself in either case. The Micro Power Refresh bit will always be cleared whenever the RESIN input is sampled Low. Therefore, when the core is initially powered up, the Micro Power DRAM refresh feature will be disabled. This bit is unaffected by the IORESET input. This bit will provide the system BIOS with a mechanism to determine whether or not the system DRAM data has been retained after a reset (IORESET) has occurred. If Self-Refresh mode is selected and enabled for Micro Power Off mode, then when Micro Power Off mode is exited, the ELANSC300 microcontroller will properly force a CAS-before-RAS refresh cycle to cause the DRAMs to exit the Self-Refresh mode. The ELANSC300 microcontroller then transitions to the normal CAS-before-RAS refresh mode. This functionality is exactly the same as the Self-Refresh mode exit when the CPU Clock Stopped mode is exited. The ELANSC300 microcontroller generates one CAS-before-RAS refresh cycle to force the DRAM to exit the Self-Refresh mode. This is also true for the Micro Power DRAM refresh feature. The timing diagrams in Figure 34 and Figure 35, on page 101, show the sequence required to guarantee a proper transition into the Micro Power state. This sequence is especially critical when the DRAM refresh option is selected. Note that the power pins of the ELANSC300 microcontroller must be kept stable for some time after the IORESET input has gone active. "Stable" means that these power pins should remain at least at their VCC (min) value for the specified time indicated in Table 51 on page 99. RESIN and IORESET The ELANSC300 microcontroller has two reset inputs to support the Micro Power Off mode. These two inputs are RESIN and IORESET. If Micro Power off mode is not to be used, the system designer should drive these two inputs from a common power-on reset source. Note that the RESIN signal is a 3.3-V only input and is not 5-V safe. For more information, see Table 24 on page 59. RSTDRV Signal Timing RSTDRV is High True output of the ELANSC300 microcontroller and is a function of the internal core's reset state, the state of the RESIN and IORESET signals, and the value for the PLL start-up timer in the Clock Control Register (Index 8Fh). (See "Loop Filters" on page 97 for more information.) RSTDRV indicates that the PLLs are gated off from the core and prevents the CPU from executing instructions until the PLL outputs have stabilized. RSTDRV is asserted immediately whenever VCC power is applied and either RESIN or IORESET is asserted. The pulse width of RSTDRV may vary and is determined by the PLL start-up timer and whether or not IORESET and/or RESIN is deasserted (i.e., cold boot versus warm reset or Micro Power Off mode exit). On a cold boot, when RESIN is asserted while power is applied to the VCC inputs and then deasserted after time delay (t1), the RSTDRV is immediately asserted when power is applied, and then held True until RESIN and IORESET are deasserted. Because the assertion of RESIN causes all the configuration registers to be reset to their default values, the PLL start-up time value in the Clock Control Register is set to 4 ms and is insufficient time for the PLLs to start up. This is why the VCCto-RESIN timing specification (t1) of 1 second is required to allow sufficient time for the crystal and the PLLs to power up and stabilize before RESIN and IORESET allow RSTDRV to be deasserted. On a warm reset, the power stays on and the VCC inputs are already powered up while the PLLs are either powered and running or gated off. RSTDRV is asserted quickly after RESIN is asserted, with the pulse width also determined by the RESIN pulse width, because the default PLL start-up timer has a value of 4 ms. It is therefore recommended that the system design guarantees at least a minimum RESIN pulse width of 250 ms for warm resets. On a wake-up from Micro Power Off mode, VCC and AVCC power to the core is maintained active, and the Clock Configuration Register value for the PLL start-up timer is preserved, but power is removed from all the other VCC inputs, and the PLLs are gated off. RSTDRV is asserted internally, and the output is driven active as soon as VSYS is powered up. When IORESET is first asserted to go into Micro Power Off Mode, RSTDRV is immediately asserted High. When power is removed from the VSYS input (which is also VCCIO for RSTDRV), the voltage level of RSTDRV begins to decay at the same rate as VSYS until it reaches approximately 0.7 V, where it remains while in Micro Power Off mode. This indicates that RSTDRV is still asserted internally inside the microcontroller and is attempting to drive the external pin High, but is unable to without power applied to its I/O driver. When exiting Micro Power Off
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY mode, as soon as VSYS is powered up, RSTDRV is immediately driven High and will remain High until the IORESET signal is deasserted and the preserved programmed value in the PLL start-up timer has expired. Force Term Figure 4 on page 57 shows the schematic diagram, and Table 24 shows the function of the IORESET, RESIN, and Force Term. When in Micro Power Off mode, it is important not to back power any of the powered-off internal power planes. Table 2-Table 11 show Micro Power Off Mode Implementation The system should not be powered up directly into Micro Power Off mode. The system must be allowed to fully power up into High Speed mode upon initial power application of any power source. If a battery has insufficient power for the ELANSC300 microcontroller to initialize into High Speed mode, the system design must first power up the ELANSC300 microcontroller from the main source, and not allow the chip to be powered from the battery until after it is fully initialized in High Speed mode and properly transitioned into Micro Power Off mode. This requirement presents an issue when using (for example) a 3-V Lithium battery cell as a back-up power source to prevent the RTC from losing its contents during Micro Power Off mode. If the battery is installed before any other power sour ce is available, the requirement cannot be met because such a small battery is incapable of supplying sufficient power to fully initialize the system. The ELANSC300 microcontroller comes up in an undefined state, perhaps drawing sufficient current to drain the battery. the VCCIO and VCC clamp voltage sources for each signal pin. Ensure that all signals, which are either driven by (VCCIO) or clamped to (VCC Clamp) a powered-off voltage source, are also either powered off or driven Low. PGP Pins PGP2 and PGP3 can be programmed to be set to a pre-defined state for Micro Power Off mode. For more information, see the ElanTMSC300 Microcontroller Programmer's Reference Manual, order # 18470. The ELANSC300 microcontroller backup power source should be installed only after the system is powered by the main power source prior to a transition into Micro Power Off mode. When the system has transitioned into Micro Power Off mode properly, the simultaneous benefits of low power consumption while maintaining RTC data such as time, date, and system configuration can be realized.
Note: The timing sequence and specifications for power-up, entering, and exiting Micro Power Off mode must be met. The timing specifications are shown in Table 51 on page 99. For more information, see the Elan TM SC300 and ElanTMSC310 Microcontrollers Solution For Systems Using a Back-up Battery Application Note, order #20746 and the Troubleshooting Guide for Micro Power Off Mode on ElanTMSC300 and ElanSC310 Microcontrollers and Evaluation Boards Application Note, order #21810.
Table 24.
IORESET 0 RESIN 0 Force Term Active
Internal I/O Pulldown States
Comments This condition occurs when any power source is initially turned on. The ELANSC300 microcontroller's core and analog VCC is transitioning to on and RESIN is active (the initial power-up state). See the Micro Power Off Mode Implementation section below for more details. This condition occurs when the core and analog VCC is stable, the RESIN pin has been inactive, and the primary power supply outputs are off (the normal Micro Power Off state). This condition should be treated as condition 0,0 above. This occurs when the secondary power supply is on, the RESIN input is inactive, and the primary power supply is on and has deasserted IORESET (normal system operating state).
0
1
Active
1 1
0 1
Active Inactive
ElanTMSC300 Microcontroller Data Sheet
59
PRELIMINARY
Core Peripheral Controllers
The ELANSC300 microcontroller includes all the standard peripheral controllers that make up a PC/AT system, including interrupt controller, DMA controller, counter/timer, and ISA bus controller. For more information, see Chapter 4 of the ElanTMSC300 Microcontroller Programmer's Reference Manual, order #18470. Interrupt Controller The ELANSC300 microcontroller interrupt controller is functionally compatible with the standard cascaded 8259A controller pair as implemented in the PC/AT. The interrupt controller block accepts requests from peripherals, resolves priority on pending interrupts and interrupts in service, issues an interrupt request to the processor, and provides the interrupt vector to the processor. The two devices are internally connected and must be programmed to operate in Cascade mode for operation of all 15 interrupt channels. Interrupt controller 1 occupies I/O addresses 020h-021h and is configured for master operation in Cascade mode. Interrupt controller 2 occupies I/O addresses 0A0h-0A1h and is configured for slave operation. Channel 2 (IRQ2) of interrupt controller 1 is used for cascading and is not available externally. The output of Timer 0 in the counter/timer section is connected to Channel 0 (IRQ0) of Interrupt controller 1. IRQ0 can be programmed to generate an SMI. See Chapter 1 of the ElanTMSC300 Microcontroller Programmer's Reference Manual, order #18470. Interrupt request from the Real-Time Clock is connected to Channel 0 (IRQ8) of Interrupt Controller 2. IRQ13 is reserved for the coprocessor in a PC/AT system and is unavailable on the ELANSC300 microcontroller. The other interrupts are available to external peripherals as in the PC/AT architecture via the IRQ15, IRQ14, IRQ12-IRQ9, IRQ7-IRQ3, and IRQ1 inputs. Other sources of interrupts are SMI/NMI and the PIRQ1- PIRQ0 inputs. The ELANSC300 microcontroller interrupt controller has programmable sources for interrupts. These programmable sources are controlled by the configuration registers. For more information, see Chapter 5 of the ElanTM SC300 Microcontroller Programmer's Reference Manual, order #18470. The Interrupt controller provides interrupt information to the ELANSC300 microcontroller power management unit to allow the monitoring of system activity. The ELANSC300 microcontroller power management unit can then use the interrupt activity to control the Power Management mode of the ELANSC300 microcontroller. For more information, see Chapter 1 of the
Elan TM SC300 Microcontroller Programmer's Reference Manual, order #18470.
DMA Controller The ELANSC300 microcontroller DMA controller is functionally compatible with the standard cascaded 8237 controller pair. Channels 0, 1, 2, and 3 are externally available 8 bit channels. DMA Channel 4 is the cascade channel. Channels 5, 6, and 7 are externally available as 16 bit channels. All the DMA channels are masked off on hardware reset or when writing the DMA master reset register.
Note: To enable the master to percolate the request to the CPU, you must also unmask the cascade channel (0) on the master.
The ELANSC300 microcontroller supports the powersaving clock stop feature that causes the clock to the DMA controller to stop except when actually needed to perform a DMA transfer. For more information about clock states and programmable clock frequencies, see Table 23 on page 54. The ELANSC300 microcontroller supports Single, Block, and Demand transfer modes; however, software-initiated DMA requests, Cascade mode for additional external DMA controllers, and Verify mode are not supported. For more information about the DMA controller, see the ElanTM SC300 Microcontroller Programmer's Reference Manual, order #18470. Counter/Timer The ELANSC300 microcontroller's counter/timer is functionally compatible with the 8254 device. A 3-channel, general-purpose, 8254 compatible, 16-bit counter/ timer is integrated into the ELANSC300 microcontroller. It can be programmed to count in binary or in Binary Coded Decimal (BCD). Each counter operates independently of the other two and can be programmed for operation as a timer or a counter. All three are controlled from a common set of control logic, which provides controls to load, read, configure, and control each counter. All of the 8254 compatible counter/timer channels are driven from a common clock that is internally generated from the LS_PLL 1.1892-MHz output. The output of Counter 0 is connected to IRQ0.
Additional Peripheral Controllers
The ELANSC300 microcontroller also integrates three other peripheral controllers commonly found in PCs, but not considered part of the "core peripherals," namely a serial port or a Universal Asynchronous Receiver Transmitter (UART), a real-time clock (RTC),
60
ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY and a parallel port. See Chapter 4 of the ElanTMSC300 Microcontroller Programmer's Reference Manual, order #18470. 16450 UART The ELANSC300 microcontroller chip includes a UART, providing ELANSC300 microcontroller systems with a serial port. This serial controller is fully compatible with the industry-standard 16450. In handheld systems, this port can connect to the pen input device or to a modem. Real-Time Clock The ELANSC300 microcontroller contains a fully 146818A-compatible real-time clock (RTC) implemented in a PC/AT-compatible fashion. The RTC drives its interrupt to power-management logic. The RTC block in the ELANSC300 microcontroller consists of a time-of-day clock with alarm and 100-year calendar. The clock/calendar can be represented in binary or BCD. It has a programmable periodic interrupt, and 114 bytes of general purpose static RAM (an extension of the 146818A standard, see the programmer's reference manual for more details). Parallel Port The ELANSC300 microcontroller parallel port is functionally compatible with the PS/2 parallel port. The ELANSC300 microcontroller parallel port interface provides the parallel port control outputs and status inputs, and also the control signals for the parallel port data buffers. The parallel port data path is external to the ELANSC300 microcontroller. This interface can be configured to operate in either a Unidirectional (normal) mode or Bidirectional (EPP) mode. The unidirectional parallel port requires only one external component, the parallel port data latch. This latch is used to latch the data from the data bus and drive the data onto the parallel port data bus, as shown in Figure 5. When the ELANSC300 microcontroller parallel port is configured for Bidirectional mode operation, the PPDWE pin is reconfigured via firmware to function as the Parallel Port Data Register address decode (PPDCS). The PPOEN output from the ELANSC300 microcontroller is controlled via the Parallel Port Control Register Bit 5. This signal is then used to control the output enable of the external parallel port data latch. By setting this bit, the parallel port data latch is disabled, and then data can be transferred from an external parallel port device into the ELANSC300 microcontroller through an external 244 type buffer. A typical bidirectional Parallel Port Data Bus implementation is shown in Figure 6. If the VCC5 supply pins are connected to a 5-V power supply, then the Parallel Port control signals will be driven by 5-V outputs and can be connected directly to the parallel port connector. If VCC5 is connected to 3.3 V, the parallel port control signals should be translated to 5 V. The ELANSC300 CPU also supports Enhanced Parallel Port (EPP) mode. The EPP mode pins are defined in Table 25.
Note: If PCMCIA write enable (PCMCWE) and PCMCIA output enable (PCMCOE) are used, the parallel port signals INIT and SLCTIN are not available.
Table 25. Parallel Port EPP Mode Pin Definition
Normal Mode STRB EPP Mode WRITE Description EPP write signal. This signal is driven active during writes to the EPP data or address register. EPP data strobe. This signal is driven active during reads or writes to the EPP data register. EPP address strobe. This signal is driven active during reads or writes to the EPP address register. EPP interrupt. This signal is an input used by the EPP device to request service. EPP wait. This signal is used to add wait states to the current cycle. It is similar to the ISA IOCHRDY signal.
AFDT
DSTRB
SLCTIN 374 Octal D Flip Flop SD7-SD0 D Q Parallel Port Data Bus ACK
ASTRB
INTR
BUSY PPDWE CLK OE
WAIT
Figure 5. ELANSC300 Microcontroller Unidirectional Parallel Port Data Bus Implementation
In Normal mode, the outputs shown in Table 25 function as open-collector or open-drain outputs. In EPP mode, these outputs must function as standard CMOS outputs that are driven High and Low. Figure 6 shows the design that should be used to support EPP mode.
ElanTMSC300 Microcontroller Data Sheet
61
PRELIMINARY
373 Octal D Transparent Latch
SD7-SD0
D
Q
Parallel Port Data Bus
EN PPOEN OE
PPDCS IOW
244 type buffer
Y
A
ENB IOR
Figure 6. The ELANSC300 CPU Bidirectional Parallel Port and EPP Implementation
Parallel Port Anomalies
General The ELANSC300 microcontroller parallel port can be physically mapped to three different I/O locations or can be completely disabled. These I/O locations are 3B(x)h, 37(x)h, and 27(x)h. Typically the system BIOS or a software driver sets up the port at system boot time. Generally, LPT1 is set up by software to be associated with IRQ7, and LPT2 (and LPT3 if desired) is set up to be associated with IRQ5. In the ELANSC300 microcontroller, the parallel port is always associated with IRQ7. This cannot be changed regardless of the I/O location to which the parallel port is mapped. Local Bus or Maximum ISA Configuration When the ELANSC300 microcontroller is configured for some bus mode other than the internal CGA controller option, the system BIOS should disable the internal video controller at boot time. This is done by setting bit 5 of the Screen Control Register 2, Index 19h in the CGA Index address space. Control Register 1, Index 20h in the CGA Index address space, controls the parallel port mapping. When the internal CGA controller is disabled, Control Register 1 cannot be accessed until the part is reset. Therefore, once the internal CGA controller has been disabled, the parallel port cannot be remapped. This can cause the system boot sequence to require modification such that the parallel port is set up prior to the disabling of the internal video controller. In addition, any software driver or setup utility which was loaded after the internal video controller was disabled would not have the ability to remap the parallel port location if it was required. For more information about parallel ports, see Chapter 4 of the ElanTMSC300 Microcontroller Programmer's Reference Manual, order #18470.
PC/AT Support Features
The ELANSC300 microcontroller provides all of the support functions found in the original PC/AT. These include the Port B status and control bits, speaker control, extensions for fast reset, and A20 gate control. (Fast CPU reset and fast A20 gate functions are controlled by either the Miscellaneous 1 Register, Index 6Fh, or port 92h). For more information, see Chapter 4 of the Elan TM SC300 Microcontroller Programmer's Reference Manual, order #18470. The ELANSC300 microcontroller also includes support for port B, and a miscellaneous PC/AT register that allows direct programming of the speaker via the SPK line. In addition, the ELANSC300 microcontroller also generates a chip select and clock source for an external, standard 8042 keyboard controller or the PC/XT keyboard feature. For more information, see Appendix B of the ElanTMSC300 Microcontroller Programmer's Reference Manual, order #18470. Port B and NMI Control Port B is a PC/AT-standard miscellaneous feature control register that is located at I/O address 061h. The
62
ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY lower 4 bits of the 8-bit register are read/write control bits that enable or disable NMI check condition sources and sound generation features. The top, or most significant, 4 bits are read/write bits that return status and diagnostic information and control the PC/XT keyboard interface. There is a master NMI enable function provided that can inhibit any NMIs from reaching the CPU regardless of the state of the individual source enables. This master NMI control is located as a single bit (7) of the register at I/O address 070h. The default value for the NMI enable bit is 1, which inhibits NMI generation.The NMI enable bit (7) is a write-only bit, and is active Low. The remaining bits of the register located at 070h (6-0) control the RTC function. Because the RTC portion of this register is only 7 bits wide and is also write only, there is no conflict between the two functions. This register is discussed in more detail in the RTC section of Chapter 4 of the ELANSC300 Microcontroller Programmer's Reference Manual, order #18470. Speaker Interface The PC/AT standard tone generation interface for the system speaker is implemented in the ELANSC300 microcontroller. There are two data paths to the SPKR pin of the device. The first path is driven by the output Channel 2 of the internal 82C54 counter/timer. The counter/timer can be programmed in various ways to generate a waveform at the output, OUT2. Also, the gate input of timer Channel 2 is controlled by the T2G bit in Port B. The timer gate can be used to inhibit tone generation by the timer channel. The second path is driven directly by the SPK bit in port B. This bit can be manipulated by the CPU to generate almost any digital waveform at the SPKR pin. Fast A20 Address Control With the ELANSC300 microcontroller, full Real mode address compatibility requires that address rollover at the 1-Mbyte address boundary be handled the same way as the early 8088-based PCs were handled. This requires the system address line 20 to have the capability of being forced to 0 during Real mode execution. Control of the A20 line is supported from multiple sources. The A20G signal in PC/AT systems is normally connected to an output of the PC/AT keyboard controller. A logic High on this input forces the pass through of the CPU's A20 onto the internal system address bus. A logic Low on this input forces the system address bus A20 line Low, as long as the internal A20 gate control is not being utilized. The ELANSC300 microcontroller provides a high-performance method for controlling the system A20 line, independent of the relatively slow PC/AT keyboard controller. This internal A20 gate control is generated by the Miscellaneous 1 Register, Index 6Fh, and Port 92h. For more information, see the Elan TM SC300 and ElanSC310 Microcontrollers GATEA20 Function Clarification Application Note, order #21811. Reset Control An external hardware reset is required in order to correctly initialize internal logic after system power-up. See the required timings in Table 51 on page 99. System power supplies typically have a POWERGOOD output signal that is used as an active Low asynchronous reset input for the device. IORESET is intended to be driven by a POWERGOOD-compatible signal. When IORESET is driven Low, the ELANSC300 microcontroller resets all of its internal logic with the exception of the RTC Valid Data/Time bit (Register D, RTC Index 0Dh, bit 7) and some internal register configuration bits. The RESIN input is intended to be driven by a signal that indicates that the battery back-up source has been disconnected. When RESIN is driven Low, the ELANSC300 microcontroller resets all of its internal logic. The RESIN input buffer is a Schmitt trigger for tolerance of slow rise and fall times on the signal. RESIN and IORESET are internally synchronized to the CPU clock to provide the internal hardware reset. For more information, see Table 24 on page 59 and "Micro Power Off Mode" on page 55. Besides the device hardware reset, the internal CPU has several other possible reset sources. These other sources only generate CPU reset. In a standard PC/AT-type system, an RC (CPU Reset) pin is typically connected to an output of the 8042 keyboard controller. Also, an internal configuration register can be used to reset the CPU in less time than that required by the external keyboard controller. The internal reset is controlled by the Miscellaneous 1 Register, Index 6Fh, and Port 92h. The ELANSC300 microcontroller provides both of the CPU reset functions described above and also triggers a CPU reset upon processor shutdown. If the CPU reaches a state where it cannot continue to execute because of faults and error conditions, it will issue a status code indicating shutdown, and the CPU will halt operation with no means of continuing except for a reset. If this shutdown status is detected, a 16 clock minimum pulse width reset is automatically sent to the CPU.
ElanTMSC300 Microcontroller Data Sheet
63
PRELIMINARY
* B U F B U F PCMCIA * B U F B U F PCMCIA
*
1 Mbyte System Memory 3.3 V or 5 V MA10-MA0 512K x 8 D15-D8 MA10-MA0 512K x 8 D7-D0 *
RAS CAS WE Serial Port MA10-MA0 D15-D0 MAX241 Slot A Control Elan Slot B Control SC300 Microcontroller SA12-SA0 Control Keyboard Controller (8042) SA23-SA13 B SD15-SD0 U F
ROM/FLASH BIOS
Video SRAM
DSMD7-DMSD0 DSMA14-DMSA0
ROM/FLASH DOS
LCD
L A T C H
Miscellaneous I/O Control
Parallel Port
Note: *Optional
Figure 7. Typical System Block Diagram (Internal LCD Controller)
64
ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
LCD, Local Bus, or Maximum ISA Bus Controller
D e p e n d i n g o n t h e c o n fi g u r a t i o n c h o s e n , th e ELANSC300 microcontroller's pin functionality will differ. The three different options are Internal CGA Controller, Local Bus, and Maximum ISA Bus modes. The pin options are selected upon power-up reset. Only Internal CGA, Local Bus, or Maximum ISA Bus mode is available in a particular design. Both Internal CGA and Local bus modes do, however, provide a subset of the ISA bus. The three sets of pin descriptions are described in "Alternate Pin Functions Selected Via Firmware" on page 71. Internal CGA Controller Option The internal video controller is fully 6845 compatible, supporting up to 640 x 200 pixel LCD panels. This option supports an external 32-Kbyte SRAM for video memory. The smallest subset of the ISA bus is available when using the internal CGA controller. Local Bus Option The local bus interface is integrated with the memory controller and the ISA bus controller, and it permits fast transfers to and from external local bus peripherals, such as video controllers. The local bus option is basically an Am386SXLV microprocessor local bus with an LDEV, LRDY, and CPUCLK added. Additional ISA bus signals are available in this mode.
Maximum ISA Bus Option The Maximum ISA option provides the most ISA bus signals of any of the ELANSC300 microcontroller bus options. Since master cycles and ISA refresh are not necessary in handheld designs, the ELANSC300 microcontroller does not provide these signals in any bus mode. The SYSCLK output from the ELANSC300 microcontroller is a clock that is normally only used for the external keyboard controller if one exists. This clock is 9.2 MHz and can be stopped completely. This clock is not related to any of the ISA bus cycle timings. The ISA bus cycle timings vary depending on the clock speed selected for the internal ISA bus clock. Internal Resistors The ELANSC300 microcontroller's internal pull-down and pull-up resistors are approximately 100-K 50% tolerance. They don't provide the level of termination that may be necessary to meet design noise margins or the timing and termination requirements for different bus specifications (e.g., ISA bus or local bus). The internal pull-up and pull-down resistors only provide adequate termination for when the input is floating and is in a very low noise environment, or for systems where power consumption is too critical to allow for the additional current associated with stronger pullups. Because of this, it is recommended that the designer use the external pull-up and pull-down resistors (shown in Table 26) on signals with critical timing or noise immunity requirements. The external pull-up and pull-down resistors are also recommended for additional design margin, provided that space and power consumption are not major issues.
Table 26.
Signal Name PIRQ0 (PIRQ0/IRQ3) PIRQ1 (PIRQ1/IRQ6) IRQ1 IOCHRDY IOCS16 [LCDDL0] MCS16 [LCDDL1] IRQ14 [LCDDL2] DTR/CFG1 RTS/CFG0 IORESET
External Resistor Requirements
Internal CGA Pin No.
194 193 195 192 196 197 198 92 93 140
Local Bus Pull Up
10K 10K 10K 1K 1K[-] 1K[-] 10K
Maximum ISA Pull Up
10K 10K 10K 1K 1K[-] 1K[-] 10K 100K 1 1 1 2 2 10K
Pull Up
10K 10K 10K 1K 1K[-] 1K[-] 10K[-]
Pull Down
Pull Down
Pull Down
Notes
100K 100K 10K
10K 100K 10K 10K
ElanTMSC300 Microcontroller Data Sheet
65
PRELIMINARY Table 26.
Signal Name LVEE (IRQ15/IRQ15) M (IRQ4/IRQ4) LCDD2 (IOCHCHK/IOCHCHK) DSWE (PULLUP/PULLUP) FRM (IRQ12/IRQ12) CP2 (PULLUP/IRQ10) DSMA1 (PULLUP/IRQ7) DSMD0 (LDEV/RESERVED) LCDD3 (DRQ1/ DRQ1) LCDD1 (DRQ5/ DRQ5) CP1 (PULLDN/ IRQ5) DSMD7 (ADS/0WS) DSMD3 (BHE/IRQ9) DSMD2 (BLE/IRQ11) DSMA3 (CPUCLK/PULLUP) DSMA0 (NC/PULLUP) DSMD6 (D/C / DRQ0) DSMD5 (M/IO / DRQ3) DSMD4 (W/R / DRQ7) DSMD1 (LRDY / DRQ6) DRQ2 [TDO] BVD2_A BVD1_A BVD2_B BL1 BL2 BL3 BL4 SOUT RST_A RST_B BVD1_B WAIT_AB CD_A CD_B
External Resistor Requirements (Continued)
Internal CGA Pin No.
182 173 177 183 181 179 164 148 174 175 178 172 168 167 162 165 171 170 169 166 76 113 114 119 106 107 108 109 94 133 127 120 115 110 116 10K 10K 10K 10K 100K 100K 10K 10K 10K 10K 10K 10K 10K 100K 100K 100K 100K 10K 10K 10K 10K 100K 100K 100K 100K 10K 100K 100K 10K 10K 10K 10K 100K 100K 4 4 4 4 1K 10K 10K 10K 10K 100K 100K 100K 100K
Local Bus Pull Up
10K 10K 1K 100K 10K 1K 10K 1K 10K 10K 10K
Maximum ISA Pull Up
10K 10K 1K 100K 10K 10K 10K
Pull Up
Pull Down
Pull Down
Pull Down
Notes
10K 10K 10K 1K 10K 10K 1M 1M 10K 10K 10K 10K 10K
3 3
3 3 3 3 3 4 4 4 5 5 5 5
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY Table 26.
Signal Name RDY_A RDY_B WP_A WP_B DCD DSR SIN CTS RIN STRB AFDT INIT SLCTIN ERROR ACK BUSY PE SLCT PGP0 PGP1 ACIN
External Resistor Requirements (Continued)
Internal CGA Pin No.
111 117 112 118 98 97 99 96 100 83 80 89 84 86 88 85 82 87 189 188 101
Local Bus Pull Up
10K 10K 10K 10K 1M 1M 1M 1M 1M 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
Maximum ISA Pull Up
10K 10K 10K 10K 1M 1M 1M 1M 1M 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
Pull Up
10K 10K 10K 10K 1M 1M 1M 1M 1M 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
Pull Down
Pull Down
Pull Down
Notes
4 4
100K 100K 10K
100K 100K 10K
100K 100K 10K
6 6 5
Notes: All pull-up and pull-down resistor requirements are specified in ohms. 1. A [-] implies that for this "programmable" pin function, no external termination is required. 2. This pin is an "alternate pin function select input" that is sampled at reset. This pin functions as a normal serial port output after RESIN and IORESET are deasserted. 3. When this pin's function is a DMA request input, it should be terminated with a pull-down resistor if not connected to an external device that drives to a known state. 4. If this ELANSC300 microcontroller input is driven directly with a logic gate, then no external termination is required at the ELANSC300 microcontroller pin. The termination on the PCMCIA socket signal is still required per the PCMCIA 2.1 specification. 5. If this ELANSC300 microcontroller input is always driven to a known state, then no external termination is required. 6. If the pin is configured as an input, it should be terminated with a discrete pull-up or pull-down resistor, or it should always be driven to a known state.
ElanTMSC300 Microcontroller Data Sheet
67
PRELIMINARY
ALTERNATE PIN FUNCTIONS
To provide the system designer with the most flexibility, the ELANSC300 microcontroller provides a means for reconfiguring some of the pin functions, depending on the system requirements. Reconfiguration of the ELANSC300 microcontroller pin functions is accomplished in one of two ways, depending on the pin functions that are to be reconfigured. To select the internal LCD controller, CPU local bus interface, or maximum ISA bus interface, the state of the DTR and RTS pins are sampled on the rising edge of the RESIN and IORESET signals when power is first applied to the ELANSC300 microcontroller. This is shown in Figure 8. After power has been initially applied and RESIN and IORESET are deasserted, additional assertions of IORESET while RESIN = 1 will not cause the pin configurations to change. However, the pin configuration inputs are always sampled in response to RESIN assertions. Table 27 shows the pin states at reset to enable the three different pin configurations involving the LCD controller, Local Bus, and Maximum ISA Bus. The bus configuration selected can be read in bits 5-6 of the Memory Configuration 1 Register, Index 66h, after the reset.
Table 27. Bus Option Select Bit Logic
Bus Selected Internal LCD Local Bus Full/Maximum ISA DTR/CFG1
0 1 X
RTS/CFG0
0 0 1
The second method of reconfiguring ELANSC300 microcontroller pin functions is accomplished by programming the internal configuration registers. This method is used to configure the following functions: n DRAM or SRAM main memory interface n Dual-scan LCD interface n Unidirectional or bidirectional parallel port n The clock source driving the X1OUT [BAUDOUT] pin n PCMCIA memory commands n 14.336-MHz clock
VCC RESIN and IORESET DTR and RTS sampled at the rising edge of RESIN and IORESET
DTR
RTS
Notes: This is shown to illustrate when CFG0 and CFG1 are sampled and is not intended to be used for reset timings. For reset timings, refer to Table 51 on page 99
Figure 8.
Bus Option Configuration Select
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
CPU Local Bus Interface versus Internal LCD Interface
The tables of this section are brief descriptions of the alternate pin functions/names and the pin name of the Internal LCD mode function that the alternate function replaces. The CPU Local Bus Interface alternate functions are configured via the DTR and RTS pin states when the ELANSC300 microcontroller is reset.
Table 28.
CPU Local Bus Interface Pin Name A23-A12
Pins Shared Between CPU Local Bus and Internal LCD Interface Functions
Pin Type CPU Local Bus Interface Pin Description/Notes Local Bus Address Bus Internal LCD Controller Mode Function Pin Name DSMA14-DSMA4 LVDD DSMD7 DSMD6 DSMD5 DSMD4 DSMD3 DSMD2 DSMD1 DSMD0 DSOE DSMA3 DSMA2 Pin No.
O
145 149-155 158-161 172 171 170 169 168 167 166 148 147 162 163
ADS D/C M/IO W/R BHE BLE LRDY LDEV CPURDY CPUCLK CPURST
O O O O O O I I O O O
Address Strobe Data/Code Cycle Status signal Memory/I/O Cycle Status signal Write/Read Cycle Status signal Byte High Enable Byte Low Enable Local Device Ready Local Bus Device Acknowledge CPU Ready CPU Clock CPU Reset
Notes: 1. The SA11-SA0 pins are the lower order address lines for local bus cycles in the Local Bus Interface mode. 2. See the Table 26 on page 65 for information on required termination for Local Bus and Internal LCD Controller modes. 3. Other Internal LCD Controller mode pin functions, which are not listed in this table, change when the Local Bus mode is entered. These pins change to an ISA bus function when Local Bus mode is entered.
ElanTMSC300 Microcontroller Data Sheet
69
PRELIMINARY
Maximum ISA Interface versus Internal LCD Interface
The maximum ISA interface alternate functions are configured via the DTR and RTS pin states when the ELANSC300 microcontroller is reset.
Table 29.
Pins Shared Between Maximum ISA Bus and Internal LCD Interface Functions
Pin Type
I O I I I I I I O O O O O O I I I I I I I I O O I
ISA Interface Pin Name IOCHCHK BALE DRQ0 DRQ1 DRQ3 DRQ5 DRQ6 DRQ7 DACK0 DACK1 DACK3 DACK5 DACK6 DACK7 IRQ4 IRQ5 IRQ7 IRQ9 IRQ10 IRQ11 IRQ12 IRQ15 LA23-LA17 LMEG 0WS
ISA Interface Pin Description/Notes ISA I/O Channel Check input ISA Bus Address Latch Enable DMA Channel 0 Request DMA Channel 1 Request DMA Channel 3 Request DMA Channel 5 Request DMA Channel 6 Request DMA Channel 7 Request DMA Channel 0 Acknowledge DMA Channel 1 Acknowledge DMA Channel 3 Acknowledge DMA Channel 5 Acknowledge DMA Channel 6 Acknowledge DMA Channel 7 Acknowledge Interrupt Request input Interrupt Request input Interrupt Request input Interrupt Request input Interrupt Request input Interrupt Request input Interrupt Request input Interrupt Request input ISA Non-Latched Address Bus ISA Memory Address Decode Below 1 Mbyte Zero Wait State
Internal LCD Controller Mode Function Pin Name LCDD2 LVDD DSMD6 LCDD3 DSMD5 LCDD1 DSMD1 DSMD4 DSMA7 DSCE DSMA6 LCDD0 DSMA4 DSMA5 M CP1 DSMA1 DSMD3 CP2 DSMD2 FRM LVEE DSMA14-DSMA8 DSOE DSMD7
Pin No.
177 145 171 174 170 175 166 169 158 146 159 144 161 160 173 178 164 168 179 167 181 182 149-155 147 172
Notes: See the External Resistor Requirements section for information on required termination for Maximum ISA Bus and Internal LCD Controller modes.
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
ALTERNATE PIN FUNCTIONS SELECTED VIA FIRMWARE
The following tables contain brief descriptions of the alternate pin functions/names and the pin names of the default function that the alternate function replaces. These alternate functions are selected via system firmware only.
SRAM Interface
This alternate function is configured by setting bit 0 of the Miscellaneous 6 Register, Index 70h.
Table 30.
SRAM Pin Name [SRCS0] [SRCS1] [SRCS2] [SRCS3] Pin Type
O O O O
SRAM Interface
Default Pin Name/Function CAS0L CAS0H CAS1L CAS1H Pin No.
6 7 4 5
SRAM Interface Pin Description/Notes SRAM Bank 0 Chip Select. Low Byte SRAM Bank 0 Chip Select. High Byte SRAM Bank 1 Chip Select. Low Byte SRAM Bank 1 Chip Select. High Byte
Dual-Scan LCD Data Bus
This alternate function is configured via selecting a dual-scan LCD Panel mode in the CGA index address space at Index 18h.
Table 31.
Dual-Scan Pin Name [LCDDL0] [LCDDL1] [LCDDL2] [LCDDL3] Pin Type
O O O O
Dual-Scan LCD Data Bus
Default Pin Name/Function IOCS16 MCS16 IRQ14 SBHE Pin No.
196 197 198 143
Dual-Scan LCD Data-Bus Pin Description/Notes Dual screen data bit Dual screen data bit Dual screen data bit Dual screen data bit
Notes: In the dual-scan LCD configuration, IOCS16 and MCS16 are internally forced inactive.
Unidirectional/Bidirectional Parallel Port
This alternate function is configured via selecting either the Normal Bidirectional mode configuration or the EPP mode configuration for the parallel port in the Function Enable 1 Register, Index B0h.
Table 32.
Bidirectional Pin Pin Type Name [PPDCS]
O
Bidirectional Parallel Port Pin Description
Bidirectional Parallel Port Pin Description/Notes Default Pin Name/Function PPDWE Pin No.
90
Parallel Port data register address decode
ElanTMSC300 Microcontroller Data Sheet
71
PRELIMINARY
X1OUT [BAUD_OUT] Clock Source
The internal clock source driving out on this pin is configured via register bits of the Function Enable Registers, Indexes B0h and B1h.
Table 33.
BAUDOUT Pin Name [BAUD_OUT] Pin Type
O
X1OUT Clock Source Pin Description
X1OUT [BAUD_OUT] Pin Description/Notes Default Pin Name/Function X1OUT Pin No.
200
Serial baud rate clock
Notes: The default function of this pin is that no clock is driven out and the pin is tri-stated.
PC/XT Keyboard
The PC/XT keyboard functionality is enabled via bit 3 of PMU Control 3 Register, Index ADh.
Table 34.
PC/XT Keyboard Pin Name [XTDAT] [XTCLK] Pin Type
I/O I/O
XT Keyboard Pin Description
PC/XT Keyboard Pin Description/Notes Default Pin Name/Function 8042CS SYSCLK Pin No.
75 45
Keyboard data Keyboard clock
PCMCIA Data Path Control
Setting bit 4 of Miscellaneous 3 Register, Index BAh, enables the PCMCIA memory commands on the Parallel port pins SLCTIN and INIT.
Table 35. PCMCIA Data Path Control
PCMCIA Control Pin Name [PCMCOE] [PCMCWE] Pin Type
O O
Data Path Control Pin Description/Notes PCMCIA Output Enable PCMCIA Write Enable
Default Pin Name/ Function SLCTIN INIT
Pin No.
84 89
14-MHz Clock Source
Setting bit 3 of Miscellaneous 3 Register, Index BAh, enables the 14.336-MHz clock signal on the parallel port pin AFDT.
Table 36. 14-MHz Clock Source
14-MHz Pin Name [X14OUT] Pin Type
O
14-MHz Clock Pin Description/Notes 14.336 MHz Clock
Default Pin Name/ Function AFDT
Pin No.
80
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
ISA BUS DESCRIPTIONS
The three bus configuration options (Internal LCD controller, local bus, or maximum ISA bus) each support a somewhat different subset of the ISA bus standard. The Internal LCD controller option supports the smallest ISA subset, defined in Table 37. The Local Bus configuration supports a larger ISA subset. The additional pins supported are shown in Table 38. The Maximum ISA Bus configuration adds the pins found in Table .
Table 38. Table 37. Internal LCD Controller Bus Mode ISA Bus Functionality
Pin Name SA23-SA0 D15-D0 IOCHRDY RSTDRV MEMW MEMR IOW IOR AEN TC SYSCLK IRQ1 PIRQ0 PIRQ1 DACK2 DRQ2 IOCS16 MCS16 IRQ14 SBHE X1OUT [BAUDOUT] I/O
O B I O O O O O O O O I I I O I I I I O O
Local Bus Mode Additional ISA Bus Functionality
I/O
I I O I O I I I
Pin Name IOCHCHK DRQ1 DACK1 DRQ5 DACK5 IRQ4 IRQ12 IRQ15
Function ISA I/O Channel Check DMA Channel 1 Request DMA Channel 1 Acknowledge DMA Channel 5 Request DMA Channel 5 Acknowledge Interrupt Request Input Interrupt Request Input Interrupt Request Input
Function System Address Bus System Data Bus I/O Channel Ready System Reset Memory Write Memory Read I/O Write I/O Read DMA Address Enable Terminal Count System Clock (ISA bus timing is not derived from this clock) Interrupt IRQ1 Programmable IRQx Programmable IRQx DMA Channel 2 Acknowledge DMA Channel 2 Request I/O Device is 16 bits1 Memory Device is 16 bits1
Table 39. Maximum ISA Bus Mode Additional ISA Bus Functionality
Pin Name BALE DREQ0 DREQ3 DREQ6 DREQ7 DACK0 DACK3 DACK6 DACK7 IRQ7 IRQ9 IRQ11 0WS LA23-LA17 LMEG IRQ5 IRQ10 I/O
O I I I I O O O O I I I I O O I I
Function ISA Bus Address Latch Enable DMA Channel 0 Request DMA Channel 3 Request DMA Channel 6 Request DMA Channel 7 Request DMA Channel 0 Acknowledge DMA Channel 3 Acknowledge DMA Channel 6 Acknowledge DMA Channel 7 Acknowledge Interrupt Request Input Interrupt Request Input Interrupt Request Input Zero Wait State Request ISA Non-Latched Address ISA Memory Cycle Below 100000h Interrupt Request Input Interrupt Request Input
Interrupt Request Input1 Byte High Enable1 Video Oscillator (14.336 MHz)/ Serial Port Output
Notes: 1. These ISA functions are available in this mode as long as the internal LCD controller is not configured for a dualscan LCD panel in which case these pins would be used as additional data bits for the LCD panel. In Local Bus mode and Maximum ISA mode, the ISA function is always available.
ElanTMSC300 Microcontroller Data Sheet
73
PRELIMINARY
System Test and Debug
The ELANSC300 microcontroller provides test and debug features compatible with the standard Test Access Port (TAP) and Boundary-Scan Architecture (JTAG). The test and debug logic contains the following elements: n Five extra pins--TDI, TMS, TCK, TDO, and TRST (JTAGEN). JTAGEN is dedicated; the other four are multiplexed. n Test Access Port (TAP) controller, which decodes the inputs on the Test Mode Select (TMS) line to control test operations. n Instruction Register (IR), which accepts instructions from the Test Data Input (TDI) pin. The instruction codes select the specific test or debug operation to be performed or the test data register to be accessed. n Test Data Registers: Boundary Scan Register (BSR), Device Identification Register (DID), and Bypass Register (BPR). Test Access Port (TAP) Controller The TAP controller is a synchronous, finite state machine that controls the sequence of operations of the test logic. The TAP controller changes state in response to the rising edge of TCK and defaults to the test-logic-reset state at power-up. Reinitialization to the test-logic-reset state is accomplished by holding the TMS pin High for five TCK periods. Instruction Register The Instruction Register is a 4-bit register that allows instructions to be serially shifted into the device. The instruction determines either the test to execute or the data register to access, or both. The least significant bit is nearest the TDO output. When the TAP controller enters the capture-IR state, the instruction register is loaded with the default instruction IDCODE. This is done to test for faults in the boundary scan connections at the board level. Boundary Scan Register The Boundary Scan Register is a serial shift register from TDI to TDO, consisting of all the boundary scan register bits and control cells in each I/O buffer. Device Identification Register The Device Identification Register is a 32-bit register that contains the AMD ID code for the ELANSC300 microcontroller: 195FA003h. Bypass Register The Bypass Register provides a path from TDI to TDO with one clock cycle latency. It helps to bypass a chip completely while testing boards containing many chips. 74 ElanTMSC300 Microcontroller Data Sheet Test Access Port Instruction Set The following instructions are supported: n Sample/Preload. This instruction enables the sampling of the contents of the boundary scan registers as well as the serial loading of the boundary scan registers through TDI. n Bypass. This instruction connects TDI and TDO through a 1-bit shift register, the Bypass Register. n Extest. This instruction enables the parallel loading of the boundary scan registers. The device inputs are captured at the input boundary scan cell and the device outputs are captured at the output boundary scan cells. n IDCODE. This instruction connects the ID code register between TDI and TDO. The ID code register contains the fixed ID code value for the device. JTAG Software The ELANSC300 microcontroller uses combined bidirectional cells. The total number of shifts required to load the ELANSC300 Boundary Scan Register is 173. The following table shows the relative position of all the ELANSC300 JTAG cells. Note that: n The chain starts at PMC2 (pin 77) connected to TDI. n The chain ends at 8042CS (pin 75) connected to TDO. n The control cells are located within the chain, their relative position being indicated in the table. n The MUXed signals (TCK, TDI, TDO, and TMS) are not part of the cell chain. n Control cells are active Low. n Refer to Figure 10-22 of the IEEE 1149 standard.
PRELIMINARY Table 40. Pin No.
77 78 79 80 82 83 84 85 86 87 88 89 90 91 92 93 94 96 97 98 99 100 101 102 103 * 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 122 BL1 BL2 BL3 BL4 CD_A RDY_A WP_A BVD2_A BVD1_A WAIT_AB CD_B RDY_B WP_B BVD2_B BVD1_B ICDIR
Boundary Scan (JTAG) Cells--Order and Type Cell Type
output input input output input output output input input input input output bidir bidir bidir bidir bidir input input input input input input input input control input input input input input input input input input input input input input input input output Control cell for pins 106-155
Name
PMC2 RC A20GATE AFDT PE STRB SLCTIN BUSY ERROR SLCT ACK INIT PPDWE PPOEN DTR RTS SOUT CTS DSR DCD SIN RIN ACIN EXTSMI SUS/RES *
Cell Position
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Notes
ElanTMSC300 Microcontroller Data Sheet
75
PRELIMINARY Table 40. Pin No.
123 124 125 126 127 129 130 131 132 133 134 136 137 138 139 140 141 143 144 145 146 147 148 149 150 151 152 153 154 155 * 158 159 160 161 162 163 164 165 166 167 168 169
Boundary Scan (JTAG) Cells--Order and Type (Continued) Cell Type
output output output output output output output output output output output output output output output input input output output output output output bidir output output output output output output output control output output output output output output bidir output bidir bidir bidir bidir Control cell for pins 158-200
Name
MCEL_B MCEH_B VPP_B REG_B RST_B MCEL_A MCEH_A VPPA REG_A RST_A CA24 CA25 PMC0 PMC1 SPKR IORESET RESIN SBHE LCDD0 LVDD DSCE DSOE DSMD0 DSMA14 DSMA13 DSMA12 DSMA11 DSMA10 DSMA9 DSMA8 * DSMA7 DSMA6 DSMA5 DSMA4 DSMA3 DSMA2 DSMA1 DSMA0 DSMD1 DSMD2 DSMD3 DSMD4
Cell Position
43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85
Notes
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY Table 40. Pin No.
170 171 172 173 174 175 177 178 179 181 182 183 184 185 186 187 188 189 190 191 193 194 195 196 197 198 200 * 2 3 4 5 6 7 8 10 11 13 14 15 16 17 18
Boundary Scan (JTAG) Cells--Order and Type (Continued) Cell Type
bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir output output bidir bidir bidir bidir output input input input input bidir bidir bidir output control output output output output output output output output output output output output output output output Control cell for pins 2-51
Name
DSMD5 DSMD6 DSMD7 M LCDD3 LCDD1 LCDD2 CP1 CP2 FRM LVEE DSWE PMC4 PMC3 PGP3 PGP2 PGP1 PGP0 LPH IOCHRDY PIRQ(1) PIRQ(0) IRQ1 IOCS16 MCS16 IRQ14 CLK14_O * RAS0 RAS1 CAS1L CAS1H CAS0L CAS0H MWE MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3
Cell Position
86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
Notes
ElanTMSC300 Microcontroller Data Sheet
77
PRELIMINARY Table 40. Pin No.
19 21 24 25 26 27 28 29 30 31 32 34 36 37 38 39 40 41 42 43 44 45 46 47 49 50 51 * 54 55 56 57 58 59 60 61 62 63 64 66 67 69 70
Boundary Scan (JTAG) Cells--Order and Type (Continued) Cell Type
output output output bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir output output bidir * * * 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 output output control output output output output output output output output output output output output output output output Control cell for pins 54-103 This pin becomes TCK when JTAGEN is High. This pin becomes TDI when JTAGEN is High. This pin becomes TMS when JTAGEN is High.
Name
MA2 MA1 MA0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DOSCS ROMCS SYSCLK DACK2 AEN TC ENDIRL ENDIRH * IOR IOW MEMR MEMW RSTDRV DBUFOE SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4
Cell Position
129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
Notes
78
ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY Table 40. Boundary Scan (JTAG) Cells--Order and Type (Continued) Pin No.
71 72 73 74 75 76 SA3 SA2 SA1 SA0 8042CS DRQ2
Name
Cell Position
169 170 171 172 173
Cell Type
output output output output bidir *
Notes
This pin becomes TDO when JTAGEN is High.
JTAG Instruction Opcodes
Table 41 lists the ELANSC300 microcontroller's public JTAG instruction opcodes. Note that the JTAG Instruction Register is 4 bits wide.
Table 41.
ELANSC300 Microcontroller JTAG Instruction Opcodes
Instruction
EXTEST BYPASS SAMPLE/PRELOAD IDCODE HI-Z
Opcode
0000 1111 0001 0010 0011
ElanTMSC300 Microcontroller Data Sheet
79
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Storage Temperature ....................... -65C to +150C Ambient Temperature Under Bias ... -65C to +125C Supply Voltage VCC with Respect to VSS ................................-0.5 V to +7 V Voltage on Other Pins...............-0.5 V to (VCC +0.5 V)
Stresses above those listed may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability.
OPERATING RANGES
Operating ranges define those limits between which the functionality of the device is guaranteed.
Table 42.
DC Characteristics over Commercial and Industrial Operating Ranges (Plastic Shrink Quad Flat Pack (QFP), 33 MHz, 3.3 V)
VCCIO = 3.0 V - 3.6 V; TAMBIENT = 0C to +70C (commercial); TCASE = -40 to +85C (industrial)
Preliminary Symbol fosc PCC2 PCCSS2 VOH(CMOS) VOL(CMOS) VIH(CMOS) VIL(CMOS) ILI IIH IIL ILO Cin 3 AVCCRP-P Parameter Description Frequency of Operation (internal CPU clock) Supply Power--CPU clock = 33 MHz (VCCMEM=3.3 V) Suspend Power--CPU idle, all internal clocks stopped except 32.768 kHz Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current (0.1 VVOUTVCC) (all pins except those with internal pull-up/pull-down resistors) Input Leakage Current VIH = VCC - 0.1 V (all pins with internal pull-down resistors) Input Leakage Current (pins with internal pull-up resistors) Output Leakage Current I/O Capacitance Analog VCC ripple peak to peak VIL = 0.1 V (0.1 VVOUT VCC) IOH(CMOS) = -0.5 mA IOL(CMOS) = 0.5 mA
2.0 -0.3 VCC- 0.45 0.45 VCC+0.3 +0.8 10 60 -60 15 15 100
Min
0
Typ
Max
33
Unit
MHz mW mW V V V V A A A A pF mV
582 0.12
778
Notes: 1. Current out of a pin is given as a negative value. 2. VCC, VCC1, AVCC = 3.3 V and VCC5, VCCSYS, VCCSYS2 = 5.0 V. 3. Fc = 1 MHz.
80
ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY Table 43. DC Characteristics over Commercial and Industrial Operating Ranges (Plastic Shrink Quad Flat Pack (QFP), 33 MHz, 5 V)
VCCIO = 4.5 V - 5.5 V; TAMBIENT = 0C to +70C (commercial); TCASE = -40 to +85C (industrial)
Preliminary Symbol
fosc PCC2 PCCSB2 VOH(CMOS) VOL(CMOS) VIH(CMOS) VIL(CMOS) ILI IIH IIL ILO Cin (3) AVCCRP-P
Parameter Description Frequency of Operation (internal CPU clock) Supply Power--CPU clock = 33 MHz (VCCMEM=5 V) Suspend Power--CPU idle, all internal clocks stopped except 32.768 kHz Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current (0.1-VVOUT VCC) (all pins except those with internal pull-up/pull-down resistors) Input Leakage Current VIH = VCC - 0.1 V (all pins with internal pull-down resistors) Input Leakage Current (pins with internal pull-up resistors) Output Leakage Current I/O Capacitance Analog VCC ripple peak to peak (3.3 V only) VIL = 0.1 V (0.1 - V VOUT VCC) IOH(CMOS) = - 0.5 mA IOL(CMOS) = 0.5 mA
Min
0
Typ
Max
33
Unit
MHz mW mW V
660 0.17 VCC-0.45
862
0.45 2.0 -0.3 VCC+0.3 +0.8 10 90 -90 15 15 100
V V V A A A A pF mV
Notes: 1. Current out of a pin is given as a negative value. 2. VCC, VCC1, AVCC = 3.3 V and VCC5, VCCSYS, VCCSYS2 = 5 V. 3. Fc = 1 MHz.
Table 44.
Commercial and Industrial Operating Voltage Ranges at 25
3.0 V-3.6 V

Power Pin Name
VCC1 VCC1 AVCC1 VCC5 VCCMEM VCCSYS2
4.5 V-5.5 V
N/A N/A
Notes: 1.VCC and AVCC are 3.3 V only.
ElanTMSC300 Microcontroller Data Sheet
81
PRELIMINARY
THERMAL CHARACTERISTICS
The ELANSC300 microcontroller is specified for operation with a case temperature range from 0C to 100C for a commercial device. Table 45 shows the thermal resistance for 208-pin QFP and TQFP packages.
Table 45.
Package
QFP TQFP
Thermal Resistance (C/Watt) JT and JA for 208-pin QFP and TQFP packages
JT
4.7 7
JA vs. Airflow-Linear ft/min. (m/s) 0 (0)
33 37.4
200 (1.01)
26 31.0
400 (2.03)
25 28.5
600 (3.04)
23 26.9
800 (4.06)
22 26.6
TYPICAL POWER NUMBERS
Table 46 and Table 47 show the typical power numbers that were measured for the ELANSC300 microcontroller. These measurements reflect the part when it is configured for Maximum ISA and Internal CGA modes of operation at operating speeds of 33 MHz, 25 MHz, and 9.2 MHz. The connection of the various power sections of the part are outlined in the tables so that the designer may have some relative information for the power consumption differences between 3.3 V operation and 5 V operation. Please see the notes associated with the tables for specifics on the test conditions.
Table 46.
Power Pin Group
CPU Core I/O VCC Analog I/O Memory Sub ISA Bus Full ISA Bus
Typical Maximum ISA Mode Power Consumption
Maximum ISA Mode Pwr Off4
4.1 A OFF 19.8 A OFF OFF OFF OFF 0.08 mW
Name
VCC VCC1 AVCC VCC5 VCCMEM VCCSYS VCCSYS2 Total (mW)
Volts
3.3 5 3.3 5 3.3 5 5
33 MHz
119 mA 5.55 mA 2.58 mA 772 A 16.4 mA 16.8 mA 2.06 mA 582 mW
25 MHz
94.3mA 5.55mA 2.36 mA 680 A 12.6 mA 13.7 mA 1.57 mA 468mW
9.2 MHz
39.1mA 5.55mA 2.24 mA 434 A 4.9 mA 7.76 mA 0.9 mA 226mW
Doze2
6.12 mA 5.55 mA 1.39 mA 293 A 190 A 3.6 mA 21 A 72.7 mW 304 A 73.6 mW
Suspend3
5.7 A 0 A 19.9 A 0 A 10.5 A 0 A 0 A 0.12 mW 17 A 0.17 mW
Memory5
VCCMEM Total (mW)
5
26.5 mA 660 mW
20.3 mA 528 mW
8.75 mA 470 mW
OFF 0.08 mW
See notes on page 83.
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY Table 47. Typical Internal LCD Mode Power Consumption TA= 70C, VOLTTL = 0.4 V, VOHTTL = 2.4 V
Power Pin Group
CPU Core I/O VCC Analog I/O Memory Sub ISA Bus Full ISA Bus
Internal CGA Mode Volts
3.3 5 3.3 5 3.3 5 5
Name
VCC VCC1 AVCC VCC5 VCCMEM VCCSYS VCCSYS2 Total (mW)
33 MHz
121 mA 14.8 mA 2.62 mA 867 A 17 mA 18.9 mA 3.88 mA 656 mW
25 MHz
95.2 mA 14.8 mA 2.4 mA 765 A 13 mA 15.3 mA 3.86 mA 539 mW
9.2 MHz
40.1 mA 14.8 mA 2.24 mA 562 A 4.9 mA 8.1 mA 3.82 mA 292 mW
Doze2
6.24 mA 14.7 mA 1.4 mA 448 A 182 A 3.85 mA 3.79 mA 140 mW 300 A 141 mW
Suspend3
5.5 A 0 A 19.9 A 0 A 11.3 A 0 A 0 A 0.12 mW 17.6 A 0.17 mW
Pwr Off4
4.1 A OFF 19.8 A OFF OFF OFF OFF 0.08 mW
Memory 5
VCCMEM Total (mW)
5
26.8 mA 734 mW
20.4 mA 598 mW
7.6 mA 314 mW
OFF 0.08 mW
Notes: All measurements were obtained at typical room temperature (ambient). 1. In normal operating mode measurements, the ELANSC300 microcontroller is running the LandMark Speedcom benchmark (Version 2.00). All CPU idle cycles are run at the high-speed rate. 2. In Doze mode, the Doze mode configuration is such that the low-speed CPU clock is programmed to turn on for 64 refresh cycles upon an IRQ0 (DOS timer) generation. After 64 refresh cycles, the low-speed CPU clock is turned off again. The IRQ0 timer is set for an approximate 55 ms interval and the refresh duty cycle is approximately 15.6 s. In Doze mode, the highspeed PLL is always turned off and, in this case, the low-speed PLL and video PLLs are on to allow the IRQ0 periodic wakeup. 3. Suspend mode measurements were taken with DRAM refresh rate set at 8192 Hz (126 s). 4. Micropower measurements were taken with DRAM unpowered and the DRAM refresh rate set at 8192 Hz. 5. These measurements were taken with the memory interface powered at 5 V, rather than 3.3 V.
ElanTMSC300 Microcontroller Data Sheet
83
PRELIMINARY
DERATING CURVES
This section describes how to use the derating curves on the following pages in order to determine potential specified timing variations based on system capacitive loading. The pin characteristics tables in this document (see page 24) have a column called "Spec. Load." This column describes the specification load presented to the specific pin when testing was performed to generate the timing specification documented in "AC Switching characteristics and Waveforms" on page 98. For example, to find out the effect of capacitive loading on a DRAM specification such as MWE hold from CAS Low, first find the specification load for MWE from the pin characteristics table. The value here is 70 pF. Note the output drive type is D. Also, assume that the system DRAM interface is 3.3 V and our system load on the ELANSC300 microcontroller's MWE pin is 90 pF.
Referring to Figure 13, 3.3 V I/O Drive Type D Rise Time, a time value of approximately 9.8 ns corresponds to a capacitive load of 70 pF. Also referring to Figure 13, a time value of approximately 12.3 ns corresponds to a capacitive load of 90 pF. Subtracting 9.8 ns from the 12.3 ns, it can be seen that the rise time on the MWE signal will increase by 2.5 ns. Therefore, the MWE hold from CAS Low (min) parameter will increase from 15 ns to 17.5 ns (15 ns + 2.5 ns). If the capacitive load on MWE was less than 70 pF, the time given in the derating curve for the load would be subtracted from the time given for the specification load. This difference can then be subtracted from the MWE hold from CAS Low (min) parameter (ISNS) to determine the derated AC Timing parameter.
Table 48. I/O Drive Type Description (Worst Case) TA= 70C, VOLTTL = 0.4 V, VOHTTL = 2.4 V
I/O Drive Type
A B C D E
VCCIO (V)
3.0 4.5 3.0 4.5 3.0 4.5 3.0 4.5 3.0 4.5
IOLTTL (mA)
2.6 3.7 5.1 7.3 7.7 10.8 7.7 10.8 10.2 14.1
IOHTTL (mA)1
-3.5 -13.9 -5.2 -20.7 -8.6 -34.2 -10.3 -40.8 -13.6 -53.9
Notes:
1. Current out of pin is given as a negative value.
84
ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
12
10
8 Time (ns)
6
4
2
0 10 20 30 40 50 60 Load (pF) 70 80 90 100
Figure 9. 3.3-V I/O Drive Type E Rise Time
12
10
8 Time (ns)
6
4
2
0 10 20 30 40 50 60 Load (pF) 70 80 90 100
Figure 10.
3.3-V I/O Drive Type E Fall Time
ElanTMSC300 Microcontroller Data Sheet
85
PRELIMINARY
8
7
6
5 Time (ns)
4
3
2
1
0 10 20 30 40 50 60 70 80 90 100 Load (pF)
Figure 11.
5-V I/O Drive Type E Rise Time
9 8 7 6 Time (ns) 5 4 3 2 1 0 10 20 30 40 50 60 70 80 90 100 Load (pF)
Figure 12. 5-V I/O Drive Type E Fall Time
86
ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
20 18 16 14 12 10 8 6 4 2 0 10 20 30 40 50 60 70 Load (pF) 80 90 100 120 130 140
Time (ns)
Figure 13.
3.3-V I/O Drive Type D Rise Time
25
20
Time (ns)
15
10
5
0 10 20 30 40 50 60 70 Load (pF) 80 90 100 120 130 140
Figure 14. 3.3-V I/O Drive Type D Fall Time
ElanTMSC300 Microcontroller Data Sheet
87
PRELIMINARY
16
14
12
10 Time (ns)
8
6
4
2
0 10 20 30 40 50 60 70 80 90 100 120 130 140 150 Load (pF)
Figure 15.
5-V I/O Drive Type D Rise Time
18 16 14 12 Time (ns) 10 8 6 4 2 0 10 20 30 40 50 60 70 80 90 100 120 130 140 150 Load (pF)
Figure 16.
5-V I/O Drive Type D Fall Time
88
ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
14
12
10
Time (ns)
8
6
4
2
0 10 20 30 40 Load (pF) 50 60 70 80
Figure 17.
3.3-V I/O Drive Type C Rise Time
12
10
8 Time (ns)
6
4
2
0 10 20 30 40 Load (pF) 50 60 70 80
Figure 18. 3.3-V I/O Drive Type C Fall Time
ElanTMSC300 Microcontroller Data Sheet
89
PRELIMINARY
10 9 8 7 6 5 4 3 2 1 0 10 20 30 40 Load (pF) 50 60 70 80
Time (ns)
Figure 19.
5-V I/O Drive Type C Rise Time
9 8 7 6 Time (ns) 5 4 3 2 1 0 10 20 30 40 Load (pF) 50 60 70 80
Figure 20.
5-V I/O Drive Type C Fall Time
90
ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
25
20
Time (ns)
15
10
5
0 10 20 30 40 Load (pF) 50 60 70 80
Figure 21.
3.3-V I/O Drive Type B Rise Time
18 16 14 12 Time (ns) 10 8 6 4 2 0 10 20 30 40 Load (pF) 50 60 70 80
Figure 22. 3.3-V I/O Drive Type B Fall Time
ElanTMSC300 Microcontroller Data Sheet
91
PRELIMINARY
16
14
12
10 Time (ns)
8
6
4
2
0 10 20 30 40 Load (pF) 50 60 70 80
Figure 23.
5-V I/O Drive Type B Rise Time
14
12
10
Time (ns)
8
6
4
2
0 10 20 30 40 Load (pF) 50 60 70 80
Figure 24.
5-V I/O Drive Type B Fall Time
92
ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
35
30
25
Time (ns)
20
15
10
5
0 10 20 30 40 Load (pF) 50 60 70 80
Figure 25.
3.3-V I/O Drive Type A Rise Time
35
30
25
Time (ns)
20
15
10
5
0 10 20 30 40 Load (pF) 50 60 70 80
Figure 26. 3.3-V I/O Drive Type A Fall Time
ElanTMSC300 Microcontroller Data Sheet
93
PRELIMINARY
25
20
Time (ns)
15
10
5
0 10 20 30 40 Load (pF) 50 60 70 80
Figure 27.
5-V I/O Drive Type A Rise Time
30
25
20 Time (ns)
15
10
5
0 10 20 30 40 Load (pF) 50 60 70 80
Figure 28.
5-V I/O Drive Type A Fall Time
94
ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
VOLTAGE PARTITIONING
The ELANSC300 microcontroller supports both 3.3-V system designs and mixed 3.3-V and 5-V system designs. For 3.3-V-only operation, all supply pins (VCC, VCC1, VCC5, VMEM, VSYS, VSYS2, and AVCC) should be connected to the 3.3-V DC supply. To operate an interface at 5 V, the VCCIO pins associated with that I/O interface should be connected to 5 V. All supply pins of the same name should be connected to the same voltage plane. The different supply pins and their functions are described in this section. Refer to the Pin Characteristics section beginning on page 24 of this data sheet for the internal VCC rail (VCCIO and VCC Clamp) to which each pin is electrically attached. For more details about the information in this section, see the commercial and industrial operating voltage ranges beginning on page 80. Also see Table 51 on page 99 and its corresponding notes. "Typical Power Numbers" on page 82 details the power consumption of each of these supply pins in Maximum ISA mode or Internal LCD mode. operate at 3.3 V or 5 V, depending on the system design. VSYS2 -- This supply pin controls the operating voltage for some of the LCD/alternate function pins. This voltage pin should be connected to either 3.3 V or 5 V, depending on the type of bus option selected, the voltage threshold requirements of attached devices, and the state of the other voltage pins associated with the LCD/alternate function interface pins (i.e., VCC1 and VSYS). AVCC -- This supply pin provides power to the analog section of the ELANSC300 microcontroller. It should always be connected to a low-noise 3.3-V supply. For more information, see the DC characteristics specifications, beginning on page 80.
CRYSTAL SPECIFICATIONS
The ELANSC300 microcontroller on-chip oscillator is the primary clock source driving all of the on-chip PLL clock generators and the real-time clock (RTC) function directly. For problems with crystal startup, check that the specifications listed in this section are met, and refer to the Troubleshooting Guide for Micro Power Off Mode on ElanTMSC300 and ElanSC310 Microcontrollers and Evaluation Boards Application Note, order #21810. Externally, a parallel resonant PC/AT cut crystal (32.768 kHz), two capacitors, and two resistors are required for the oscillator to function properly. It is critical that the frequency of the oscillator circuit be as close as possible to the nominal 32.768 kHz frequency for RTC accuracy. By selecting the appropriate external circuit components, this oscillator circuit can be made to operate at very close to the nominal 32.768 kHz. Figure 29 shows the complete oscillator circuit, including the discrete component model for the crystal. In this figure, the external discrete components that must be supplied by the system designer are RF, RB, CD, CG, and XTAL. RF is the external feedback resistor for the on-chip amplifier. RB provides some isolation between the parasitic capacitance of the chip and the crystal. The value of this resistor also has a very small effect on the operating frequency of the circuit. CD and CG are the external load capacitors. The value of these capacitors, in conjunction with the other capacitive values discussed below, have the most affect on the operating frequency of this circuit. The discrete components inside the dotted line represent the circuit model for the crystal, with CO representing the crystal lead shunt capacitance. The dashed line component CSTRAY represents the stray capacitance of the printed circuit board. Typically, a crystal manufacturer provides values for all of the equivalent circuit
VCC -- These supply pins are used to provide power to the ELANSC300 microcontroller core only. They should always be connected to a 3.3-V source. VCC1 -- This supply pin provides power to a subset of the LCD/alternate, power management, and ISA interface pins. It can be connected to either a 3.3-V or 5-V source, depending on the logic threshold requirements of the external peripherals attached to these interfaces. When connected to the 5-V supply, all outputs with VCC1 as their VCCIO will be 5 V. If connected to 3.3 V, all of these outputs will be 3.3 V. VCC5 -- These supply pins are used to provide a 5-V source for the 5-V input and output pins. If the system design requires that the ELANSC300 microcontroller support 5-V tolerant inputs, then this pin should be connected to a 5-V DC source. This supply pin is the VCCIO for the Parallel Port, Serial Port, and PCMCIA interfaces. VMEM -- This supply pin controls the operating voltage of the memory interface. When connected to the 5-V supply, all outputs to the main memory will be 5 V. This includes the ELANSC300 microcontroller data bus. Therefore, translation buffers may be required when interfacing to 5-V devices on the data bus when the memory interface is operating at 3.3 V. VSYS -- These supply pins provide power to a subset of the ISA address and command signal pins, external memory chip selects, buffer direction controls, and other miscellaneous functions. They can be required to
ElanTMSC300 Microcontroller Data Sheet
95
PRELIMINARY model components for a given crystal (i.e., L1, C1, R1, and CO). In addition to these parameters, the manufacturer will provide a load capacitance specification usual l y de s ig na te d as C L . T h e l o ad c ap ac i ta n ce specification is the capacitive load at which the manufacturer has tuned the crystal for the specified frequenc y. It is ther efor e req uir ed that the load capacitance in the oscillator circuit is duplicated as closely as possible to the manufacturer's load capacitance specification. The crystal load capacitance in the circuit consists of the capacitor network CO, CSTRAY, CD, and CG. This network reduces to (CO + CSTRAY) in parallel with the series combination of CD and CG. Therefore, the desired series combination of CD and CG is equal to CL - (CO + CSTRAY), where CL is the crystal manufacturer's load capacitance specification. The series combination of CD and CG =
( C D x CG ) -------------------------- ( CD + CG )
CSTRAY is typically difficult to determine. Some value can be assumed and experimentation will determine the optimal value for CD and CG. In determining the external component values to provide the optimal operating frequency, there are some recommended limits to ensure a reasonable start-up time for the oscillator circuit. These limits are shown in Table 49.
Table 49. Recommended Oscillator Component Value Limits
Minimum RF RB CD CG 14 M 0 10 pF 10 pF Maximum 18 M 10 k 30 pF 30 pF
ELANSC300 Microcontroller X32IN (201) X32OUT (202)
RB RF
XTAL A B A CO L1 C1 R1 B
CD
CSTRAY CG
Notes: For board layout suggestions, refer to the ELANSC300 Microcontroller Evaluation Board User's Manual available in PDF format on the AMD web site.
Figure 29. X32 Oscillator Circuit
96
ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
LOOP FILTERS
Each of the Phase-Locked Loops (PLLs) in the ELANSC300 microcontroller requires an external Loop Filter. Figure 30 describes each of the Loop Filters and the recommended component values. The recommended component values are shown in Table 50. The system designer shall include the pads on the printed circuit board to accommodate the future installation/change of C2 and R1. This is recommended because the PLL performance can be affected by the physical circuit board design. In addition, future revisions of the ELANSC300 microcontroller with a modified PLL design may require the addition of these components to the system board. The component value(s) of the Loop Filter directly affect the acquisition (start up) time of the PLL circuit. With the values recommended, the approximate acquisition time is 200 ms. Therefore, the system designer should program the Clock Control Register at Index 8Fh appropriately. Bits 0, 1, and 2 set the PLL restart delay time. When the PLLs are shut off for any reason (i.e., power management), the PLL will be allowed an amount of time equal to that programmed in this register to start up before the PLL outputs are enabled for the internal device logic. A PLL restart delay time of 256 ms should be set in the Clock Control Register. The pulse width of the RSTDRV signal is adjustable based on the PLL start-up timing. See the timing specifications in Table 51 and Figure 32-Figure 35. Table 10 on page 33 shows the pin characteristics for the Loop Filters, including the reset voltage level of each pin when RESIN is active. For more information about Loop Filters, see the Troubleshooting Guide for Micro Power Off Mode on the ElanTMSC300 and ElanSC310 Microcontrollers and Evaluation Boards Application Note, order #21810.
LFx
R1
C2
C1
Figure 30.
Loop-Filter Component
Table 50. Loop-Filter Component Values
LFx 1 2 3 4 R1 0 0 0 0 C1 0.47 F 0.47 F 0.47 F 0.47 F C2 Not Installed Not Installed Not Installed Not Installed
Notes: 1. When the PLL is on, VLFx should be approximately between 1 V and 2 V.
ElanTMSC300 Microcontroller Data Sheet
97
PRELIMINARY
AC SWITCHING CHARACTERISTICS AND WAVEFORMS
The AC specifications provided in the AC characteristics tables that follow consist of output delays, input setup requirements, and input hold requirements. Figure 31 provides a key to the switching waveforms. AC specifications measurement is defined by the figures that follow each timing table. Output delays are specified with minimum and maximum limits, measured as shown. The minimum delay times are hold times provided to external circuitry. Input setup and hold times are specified as minimums, defining the smallest acceptable sampling window. Within the sampling window, a synchronous input signal must be stable for correct microcontroller operation.
OUTPUTS Will be Steady
WAVEFORMS
INPUTS Must be Steady
May Change from H to L
Will be Changing from H to L
May Change from L to H
Will be Changing from L to H
Don't Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High-Impedance "Off" State
Figure 31. Key to Switching Waveforms
AC Switching Test Waveforms
VIH = VCC VCC / 2 Test Points VCC / 2
VIL = 0
Input
Output
Notes: AC Testing: Inputs are driven at 3 V for a logic 1 and 0 V for a logic 0.
98
ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
AC Switching Characteristics over Commercial and Industrial Operating Ranges
Table 51. Power-Up Sequencing (See Figures 32, 33, 34, and 35)
Preliminary Symbol t1 t2 t3 t4 t5 t6 t7 Parameter Description All VCC valid to RESIN and IORESET inactive RESIN and IORESET inactive to RSTDRV inactive IORESET active to RSTDRV active VSYS2, VCC1, and VSYS valid delay from VCC5 VSYS2, VCC1, VSYS, and optionally VMEM valid to IORESET inactive VCC5, VSYS2, VCC1, VSYS hold time from IORESET active VCC5 hold time from VSYS2, VCC1, and VSYS inactive Notes 1, 2 2, 3 300 0 0 5 5 0 Min Typ 1 Max Unit s s ns ns s s ns
Notes: 1. This parameter is dependent on the 32-kHz oscillator start-up time. The oscillator start-up time is dependent on the external component values used, board layout, and power supply noise. See the Crystal Specifications section on page 95 for more information. 2. RESIN remains inactive during Micro Power Off mode and Micro Power Off mode exit. 3. The pulse width of RSTDRV is adjustable based on PLL startup timing. For more information, see "Loop Filters" on page 97. Voltage sequencing on power-up for the ELANSC300 microcontroller should be observed as follows: - VCC - All VCC clamp sources (VCC, VMEM, VSYS, VCC5, and AVCC) - All VCCIO sources (VCC5, VMEM, VSYS, VCC1, VSYS2, and AVCC). The reverse is true when powering down. For any particular I/O pin, the VCCIO may come up simultaneously with the VCC clamp, but should never precede the VCC clamp. Refer to the Pin Characteristics table (page 24) for detailed I/O information.
ElanTMSC300 Microcontroller Data Sheet
99
PRELIMINARY
VCC/AVCC VMEM RESIN VCC5 VSYS2 VCC1 VSYS IORESET RSTDRV t2
t4 t1
Note 1
Notes: 1. RSTDRV external driver is powered by: VCCIO = VSYS and VCC Clamp = VCC5.
Figure 32. Power-Up Sequence Timing
VCC/AVCC VMEM RESIN VCC5 VSYS2 VCC1 VSYS IORESET RSTDRV
t5 t4
Note 1
Note 2
Notes: 1. RSTDRV external driver is powered by: VCCIO = VSYS and VCC Clamp = VCC5. 2. The pulse width of RSTDRV is adjustable based on PLL startup timing. See the Loop Filters section on page 97 for more information.
Figure 33. Micro Power Off Mode Exit
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
t3 RSTDRV
Note 1
IORESET VCC5 VSYS2 VCC1 VSYS VCC/AVCC VMEM RESIN
Notes: 1. RSTDRV external driver is powered by: VCCIO = VSYS and VCC Clamp = VCC5. 2. A secondary power source could be applied at this time
Note 2
t7 t6
Figure 34. Entering Micro Power Off Mode (DRAM Refresh Disabled)
t3 RSTDRV IORESET VCC5 VSYS2 VCC1 VSYS
Note 2 Note 1
2 DRAM Refresh Cycles t7
VCC/AVCC VMEM RESIN
Notes: 1. RSTDRV external driver is powered by: VCCIO = VSYS and VCC Clamp = VCC5. 2. A secondary power source could be applied at this time
Figure 35. Entering Micro Power Off Mode (DRAM Refresh Enabled)
ElanTMSC300 Microcontroller Data Sheet
101
PRELIMINARY Table 52. DRAM Memory Interface, Page Hit and Refresh Cycle (See Figures 36 and 37)
Preliminary Symbol t30 t31 t32 t37 t38 t39 t41 t42 t43 t45 t46 t47 t48 t49 t50 t51 t53 Parameter Description MA valid setup to RAS Low MA hold from RAS Low MA setup to CAS Low CAS precharge (Page mode) MA hold from CAS active RAS to CAS delay CAS pulse width (page hit) MWE setup to CAS Low (page hit) MWE hold from CAS Low CAS cycle time (Page mode) CAS Low to D15-D0 valid (read access time) D15-D0 hold from CAS High (read) D15-D0 setup to CAS Low (write) D15-D0 hold from CAS Low (write) CAS Low to RAS Low (refresh) CAS hold from RAS Low (refresh) RAS pulse width (suspend refresh) 0 0 15 10 70 80 Notes Min 0 10 0 10 15 20 20 0 15 45 20 10,000 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: These timings are based on 33-MHz operation (70 ns or faster DRAM recommended).
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
t30
MA10-MA0
t31
RAS
t38 t32 t39 t41 t45 t37 t46 t47
CAS
t43 t42 MWE t49 t48
D15-D0 Figure 36. DRAM Timings, Page Hit
t53
RAS0
t50 t51
CAS0 MWE Figure 37. DRAM Timings, Refresh Cycle
ElanTMSC300 Microcontroller Data Sheet
103
PRELIMINARY Table 53. DRAM First Cycle Read Access (See Figure 38)
Symbol t5a CAS Low to data valid (read access time) t28a RAS Low to data valid (read access time) t30 t31 t32 t33 t34 t38 t39 t40 t41a CAS pulse width (read, first cycle) t44a CAS hold from RAS Low MA valid setup to RAS Low MA hold from RAS Low MA setup to CAS Low RAS hold from CAS Low RAS precharge from CAS High MA hold from CAS active RAS to CAS delay RAS pulse width Parameter Description Wait States 1 2 3 1 2 3 N/A N/A N/A N/A N/A N/A N/A N/A 1 2 3 1 2 3 Min 20 50 80 50 80 110 0 10 0 20 10 15 20 70 30 60 90 60 90 120 10,000 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: For more information about DRAM first cycle read wait states, see the DRAM First Cycle Wait State Select Logic table in Chapter 5 of the ElanTMSC300 Microcontroller Programmer's Reference Manual, order #18470.
Table 54.
Symbol t5b
DRAM Bank/Page Miss Read Cycles (See Figure 38)
Wait State 3 Min 35 65 80 65 95 110 30 20 10 38 38 53 30 70 10,000 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Parameter Description
CAS Low to data valid (read access time) t28b RAS Low to data valid (read access time) t29a t33 t34 t36 RAS precharge (page miss) t39 t40 RAS to CAS delay RAS pulse width CAS precharge (page miss read) RAS hold from CAS Low RAS precharge from CAS High
4 5 3 4 5 N/A N/A N/A 3 4 5 N/A
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY Table 54. DRAM Bank/Page Miss Read Cycles (See Figure 38) (Continued)
Symbol t41b CAS pulse width (read, page miss) t44b CAS hold from RAS Low t47 D15-D0 hold from CAS High (read) Parameter Description Wait State 3 4 5 3 4 5 N/A Min 45 75 90 75 105 120 0 Max Unit ns ns ns ns ns ns ns
Notes: For more information about DRAM bank miss read wait states, see the DRAM Bank Miss Wait State Select Logic table in Chapter 5 of the ElanTMSC300 Microcontroller Programmer's Reference Manual, order #18470.
t38
MA10-MA0
t31 t30 t40
t34 t36
RAS
t44a t32 t39 t41a t39 t29a t33 MWE t28a t5a t28b t5b t47 t41b t44b
CAS
D15-D0
First Cycle Bank/Page Miss
Figure 38.
DRAM First Cycle and Bank/Page Miss (Read Cycles)
ElanTMSC300 Microcontroller Data Sheet
105
PRELIMINARY Table 55. DRAM First Cycle Write Access (See Figure 39)
Symbol t5c t27d t30 t31 t32 t33 t34 t38 t39 t40 t41d CAS pulse width (first cycle, write) t43 t44d CAS hold from RAS Low (first cycle, write) t49 D15-D0 hold from CAS Low (write) MWE hold from CAS Low Parameter Description D15-D0 setup to CAS Low (write) MWE setup to CAS Low (first cycle) MA valid setup to RAS Low MA hold from RAS Low MA setup to CAS Low RAS hold from CAS Low RAS precharge from CAS High MA hold from CAS active RAS to CAS delay RAS pulse width Wait State N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 1 2 3 N/A 1 2 3 N/A Min 5 20 0 10 0 20 10 15 20 70 15 45 75 15 45 75 105 15 10,000 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: For more information about DRAM first cycle write wait states, see the DRAM First Cycle Wait State Select Logic table in Chapter 5 of the ElanTMSC300 Microcontroller Programmer's Reference Manual, order #18470.
Table 56. DRAM Bank/Page Miss Write Cycles (See Figure 39)
Symbol t5c t27c MWE to CAS Low t29b t33 t34 t36 RAS precharge t39 t40 t41c CAS pulse width (page miss write) t44c CAS hold from RAS Low (page miss write) t49 D15-D0 hold from CAS Low (write) RAS to CAS delay RAS pulse width CAS precharge (page miss write) RAS hold from CAS Low RAS precharge from CAS High Parameter Description D15-D0 setup to CAS Low (write) Wait State N/A 3 4 5 N/A N/A N/A 3 4 5 N/A N/A 3 4 5 3 4 5 N/A Min 5 65 65 80 60 20 10 38 38 53 30 70 30 60 75 60 90 105 15 10,000 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: For more information about DRAM bank miss wait states, see the DRAM Bank Miss Wait State Select Logic table in Chapter 5 of the ElanTMSC300 Microcontroller Programmer's Reference Manual, order #18470.
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
t38
MA10-MA0
t31 t30 t40
t34 t36
RAS
t44d t32 t39 t41d t29b t33 t43 t27d MWE t49 t49 t5c t5c t27c t41c t39 t44c
CAS
D15-D0
First Cycle Bank/Page Miss
Figure 39.
DRAM First Cycle and Bank/Page Miss (Write Cycles)
ElanTMSC300 Microcontroller Data Sheet
107
PRELIMINARY Table 57. Local Bus Interface (See Figure 40)
Preliminary Symbol t1 t2 t3 t4 t5 t6a t6b t7 t8 t9 t10 t11 t12 t13 CPUCLK period CPUCLK pulse width low CPUCLK pulse width high ADS delay from CPUCLK A[23-1] BLE, BHE, W/R,D/C, M/IO delay from CPUCLK LDEV valid from address or control (non-zero wait state) LDEV valid from address or control (zero wait state) LRDY valid from CPUCLK LRDY high impedance from CPUCLK CPURDY delay from CPUCLK CPURDY high impedance from CPUCLK D15-D0 setup to CPUCLK (read) D15-D0 hold from CPUCLK (read) D15-D0 valid from CPUCLK (write) Parameter Description Notes Min 14 7 7 3 5 2 2 2 0 5 0 7 0 5 0 20 15 23 20 18 12 5 26 5 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
t1
CPUCLK
t2
t3
t11
ADS
t5
t4
A23-A12
t6a t6b t6a
LDEV
LRDY
t7
t8
t8
CPURDY
t12
t9
t9
t10
D15-D0 (in)
t13
D15-D0 (out) Figure 40. Local Bus Interface
t13
ElanTMSC300 Microcontroller Data Sheet
109
PRELIMINARY Table 58. Video RAM/LCD Interface (See Figures 41 and 42)
Preliminary Symbol t81 t82 t83 t84 t85 t86 t87 t88 t89 t90 t91 t92 t93 t94 t95 t96 t97 Parameter Description DSMD hold from DSMA change Display RAM read cycle pulse width DSMD active from DSWE active DSMD setup to DSWE inactive DSMA hold from DSWE inactive DSMD hold from DSWE inactive Display RAM write cycle pulse width DSMD tri-state delay from DSOE High DSMD delay from DSOE active Panel data setup to CP2 (data clock) Panel data hold from CP2 (data clock) Panel data delay from CP2 (data clock) CP2 allowance time from CP1 (latch pulse) CP1 allowance time from CP2 FRM setup time FRM hold time DSMA setup to DSWE active 65 65 520 520 0 15 5 0 65 5 5 5 10 10 30 30 Notes Min 5 85 50 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 59.
Power Management Control Signals (Not Shown)
Preliminary
No.
Parameter Description EXTSMI pulse width SUS/RES pulse width LVDD active Low to LVEE active Low LVEE inactive to LVDD inactive
Notes
Min 10 100
Max
Units ns ns
1, 3 2, 3
Notes: 1. These timings are always controlled via refresh cycle generation and are therefore based on the programmed refresh rate for the system. LVEE active always follows LVDD active by one refresh cycle. This sequence will always occur when the system exits reset or when the system transitions from the Suspend mode to High-Speed PLL mode. The default refresh rate after reset is 15.0 s. See the ElanTMSC300 Microcontroller Programmer's Reference Manual, order #18470, for a full description of the power management unit and the refresh control mechanisms. 2. LVEE will always be forced to inactive whenever the device enters the Sleep mode, or whenever the Video PLL is forced off in Doze mode. LVEE will remain inactive in Suspend mode. LVDD will remain active until the device enters the Suspend mode, at which point it will be forced inactive. 3. The LCD panel data and control signals are all forced to a logical 0 in the power management modes that are programmed to disable the video PLL (i.e., the video PLL may be disabled in Doze, Sleep, and Suspend modes). These signals will be redriven whenever LVDD is driven active.
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
t82
t85
DSMA14-DSMA0
DSCS
DSOE
t97
t87
DSWE
t86
t81
t83 t88
t84 t89
DSMD7-DSMD0
Figure 41.
Display SRAM Timings
t94 t93
CP1
t90 t92 t91
CP2
t96 t95
FRM LCDD3- LCDD0 Figure 42. LCD Interface Timings
ElanTMSC300 Microcontroller Data Sheet
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PRELIMINARY Table 60. PCMCIA Memory Read Cycle (See Figure 43)
Preliminary Symbol t1a t1b t2 t3 t4a t4b t5 t6a t6b t7 t8 t9 t10 t11 t12 t13 t14 t15a t15b t16 Parameter Description Data setup before MEMR inactive (8 bit) Data setup before MEMR inactive (16 bit) Data hold following MEMR MEMR width time Address setup before MEMR (8 bit) Address setup before MEMR (16 bit) Address hold following MEMR MCE setup before MEMR (8 bit) MCE setup before MEMR (16 bit) MCE hold after MEMR MEMR inactive from WAIT_AB inactive WAIT_AB delay falling from MEMR WAIT_AB pulse width time ICDIR setup before MEMR ICDIR hold after MEMR DBUFOE setup before MEMR DBUFOE hold after MEMR ENDIRH, ENDIRL setup before MEMR (8 bit) ENDIRH, ENDIRL setup before MEMR (16 bit) ENDIRH, ENDIRL hold from MEMR 5 -1 0 -2 -2 170 45 -4 2, 3 4 4 2, 4 1 Notes Min 40 25 0 550 155 60 0 175 45 0 120 35 12,000 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Violates for 600 ns (3.3 V) PCMCIA read cycle only. 2. PCMCIA specifies 35 ns for a 600 ns cycle, 20 ns for 250 and 200 ns cycles, and 15 ns for a 100 ns cycle. 3. If PCMCIA is buffered, this hold time may be increased by propagation delay through the buffer. 4. If the PCMCIA address buffer is controlled via the MCE signals, the output disable/enable delay of the buffer will affect the address setup and hold from MEMR. 5. WAIT_AB asserted for longer that 10 s may cause a DRAM RAS low (max) to be violated if the "extended" PCMCIA cycle occurs during a DRAM page hit. (See the tRASC max parameter for a particular DRAM.) The RAS active timer (10 s) will not force RAS inactive while the "extended" PCMCIA cycle is occurring. These timings are based on default device settings and required initial programming. These timings may be modified via the MMS Memory Wait State 1 and 2 Registers, Index 62h and Index 50h, and the Command Delay Register, Index 60h. (See the ElanTMSC300 Microcontroller Programmer's Reference Manual, order #18470.)
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
t4a t4b
t5
SA25-SA0 REG/MCE
t6a t6b t3 t7
MEMR
t9 t10
t1a t1b t8
t2
WAIT_AB D15-D0
t11 t12
ICDIR DBUFOE ENDIRH, ENDIRL
t13 t15a t15b t14
t16
Figure 43.
PCMCIA Memory Read Cycle
ElanTMSC300 Microcontroller Data Sheet
113
PRELIMINARY Table 61. PCMCIA Memory Write Cycle (See Figure 44)
Preliminary Symbol t2 t3 t4a t4b t5 t6a t6b t7 t8a t8b t9a t9b t10 t11 t12 t13a t13b t14 Parameter Description Data hold following MEMW MEMW width time Address setup before MEMW (8 bit) Address setup before MEMW (16 bit) Address hold following MEMW MCE setup before MEMW (8 bit) MCE setup before MEMW (16 bit) MCE hold after MEMW Output Enable (MEMR) setup before MEMW (8 bit) Output Enable (MEMR) setup before MEMW (16 bit) Output Enable (MEMR) hold after MEMW (8 bit) Output Enable (MEMR) hold after MEMW (16 bit) MEMW inactive from WAIT_AB inactive WAIT_AB delay falling from MEMW WAIT_AB pulse width time DBUFOE setup before MEMW (8 bit) DBUFOE setup before MEMW (16 bit) DBUFOE hold after MEMW 1 150 50 50 Notes Min 50 500 150 60 50 175 45 40 200 100 250 150 100 35 12,000 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. WAIT_AB asserted for longer that 10 s may cause a DRAM RAS Low (max) to be violated if this "extended" PCMCIA cycle occurs during a DRAM page hit. (See the tRASC max parameter for a particular DRAM.) The RAS active timer (10 s) will not force RAS inactive while the "extended" PCMCIA cycle is occurring. These timings are based on default device settings and required initial programming. These timings may be modified via the MMS Memory Wait State Registers 1 and 2, Index 62h and Index 50h, and Command Delay Register, Index 60h. (See the ElanTMSC300 Microcontroller Programmer's Reference Manual, order #18470.)
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
t4a t4b t6a REG/MCE t6b t3 MEMW t11 WAIT_AB D15-D0 t13a DBUFOE t8a t8b MEMR t13b t14 t9a t9b t12 t10 t2 t7
t5
SA25-SA0
Figure 44.
PCMCIA Memory Write Cycle
ElanTMSC300 Microcontroller Data Sheet
115
PRELIMINARY Table 62. PCMCIA I/O Read Cycle (See Figure 45)
Version B3 Preliminary Symbol t1 t2 t3a t3b t4a t4b t5 t6a t6b t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18a t18b t19 t20 t21 Parameter Description Data setup before IOR Data hold following IOR IOR width time (8 bit) IOR width time (16 bit) Address setup before IOR (8 bit) Address setup before IOR (16 bit) Address hold following IOR MCEL setup before IOR (8 bit) MCEL setup before IOR (16 bit) MCE hold after IOR REG setup before IOR REG hold after IOR IOIS16 delay falling from Address IOIS16 delay rising from Address WAIT_AB delay falling from IOR WAIT_AB pulse width time ICDIR setup before IOR ICDIR hold after IOR DBUFOE setup before IOR DBUFOE hold after IOR ENDIRH, ENDIRL setup before IOR (8 bit) ENDIRH, ENDIRL setup before IOR (16 bit) ENDIRH, ENDIRL hold from IOR MCEH delay from IOIS16 active IOR inactive from WAIT_AB inactive 100 3 -5 0 -3 -3 170 110 -6 50 100 1, 2 1 2 Notes Min 40 0 560 280 150 115 -1 160 100 5 5 0 35 35 35 12,000 -5 5 -3 45 170 110 45 50 Max Min 40 0 490 225 150 115 50 160 100 65 5 65 35 35 35 12,000 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Version B4 Preliminary Units
Notes: 1. PCMCIA specifies 20 ns (min) for 5 V I/O cards. 2. If the PCMCIA address buffer is controlled via the MCE signals, the output disable/enable delay of the buffer will affect the address setup and hold from MEMR. 3. WAIT_AB asserted for greater that 10 s may cause a DRAM RAS low (max) to be violated if the "extended" PCMCIA cycle occurs during a DRAM page hit. (See the tRASC max parameter for a particular DRAM.) The RAS active timer (10 s) will not force RAS inactive while the "extended" PCMCIA cycle is occurring. These timings are based on default device settings and required initial programming. These timings may be modified via the Wait State Control and Command Delay Register. (See the ElanTMSC300 Microcontroller Programmer's Reference Manual, order #18470.)
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
SA15-SA0 REG MCEL MCEH
t4a t4b t8 t6a t6b t9 t7
t5
t11
t20 t3a t3b
t1
t2
IOR
t10 t21
IOIS16 WAIT_AB D15-D0 ICDIR DBUFOE ENDIRH, ENDIRL
t14 t16 t18a t18b t15 t17 t19 t12 t13
Figure 45.
PCMCIA I/O Read Cycle
ElanTMSC300 Microcontroller Data Sheet
117
PRELIMINARY Table 63. PCMCIA I/O Write Cycle (See Figure 46)
Preliminary Symbol t1 t2 t3a t3b t4a t4b t5 t6a t6b t7 t8a t8b t9 t10 t11 t12 t13 t14a t14b t15 t16 t17 Parameter Description Data setup before IOW active Data hold following IOW IOW width time (8 bit) IOW width time (16 bit) Address setup before IOW (8 bit) Address setup before IOW (16 bit) Address hold following IOW MCEL setup before IOW (8 bit) MCEL setup before IOW (16 bit) MCE hold after IOW REG setup before IOW (8 bit) REG setup before IOW (16 bit) REG hold after IOW IOIS16 delay falling from Address IOIS16 delay rising from Address WAIT_AB delay falling from IOW WAIT_AB pulse width time DBUFOE setup before IOW (8 bit) DBUFOE setup before IOW (16 bit) DBUFOE hold after IOW MCEH delay from IOIS16 active IOW inactive from WAIT_AB inactive 100 1 230 165 50 50 Notes 2 Min 25 50 440 165 175 165 50 215 160 50 230 170 50 35 35 35 12,000 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. WAIT_AB asserted for longer than 10 s may cause a DRAM RAS Low (max) to be violated if this "extended" PCMCIA cycle occurs during a DRAM page hit. (See the tRASC max parameter for a particular DRAM.) The RAS active timer (10 s) will not force RAS inactive while the "extended" PCMCIA cycle is occurring. 2. PCMCIA specifies 60 ns minimum for data setup to I/O write active. These timings are based on default device settings and required initial programming. These timings may be modified via the Wait State Control and Command Delay Registers. (See the ElanTMSC300 Microcontroller Programmer's Reference Manual, order #18470.)
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
t4a t4b
t5
t11
SA25-SA0 REG
t8a t8b t6a t6b t9
t7
MCEL MCEH
t1
IOW
t16 t10
t3a t3b
t2 t17
IOIS16
t12 t13
WAIT_AB D15-D0 DBUFOE
t14a t14b
t15
Figure 46.
PCMCIA I/O Write Cycle
ElanTMSC300 Microcontroller Data Sheet
119
PRELIMINARY Table 64. BIOS ROM Read/Write 8-Bit Cycle (See Figure 47)
Preliminary Symbol t1a t1b t2a t2b t3a t3b t4a t4b t5a t5b t6 t7 t8 t9 t10 t11a t11b t12 t13 t14 t15 Parameter Description SA stable to ROMCS active SA stable to ROMCS active SA hold from ROMCS inactive (write) SA hold from ROMCS inactive (read) ROMCS pulse width (read) ROMCS pulse width (write) MEMW active to ROMCS active MEMR active to ROMCS active ROMCS hold from MEMW inactive ROMCS hold from MEMR inactive RDDATA setup to command inactive RDDATA hold from command inactive WRDATA setup to command inactive WRDATA hold from command inactive DBUFOE active from command DBUFOE hold from MEMW DBUFOE hold from MEMR ENDIRH, ENDIRL setup before MEMR ENDIRH, ENDIRL hold from MEMR ROMCS active to command active ROMCS hold from SA 2 2 -4 65 5 50 -2 50 Notes 1 2 1 1 1 1 1 1 1 1 0 0 40 0 200 50 5 50 0 390 335 2 1 Min 55 5 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. This is the timing when ROMCS is qualified with MEMR or MEMW, (Bit 2 of the Miscellaneous 5 Register, Index B3h, = 0.) 2. This is the timing when ROMCS is configured as an address decode, (Bit 2 of the Miscellaneous 5 Register, Index B3h, = 1.) These timings are based on default wait state settings, set for three wait states in bits 4 and 7 of the Command Delay Register, Index 60h, and required initial programming. These timings may be modified via the MMS Memory Wait State 1 Register, Index 62h, and the Command Delay Register, Index 60h. (See the ElanTMSC300 Microcontroller Programmer's Reference Manual, order #18470.) For fast ROMCS (BIOS ROM) accesses, set bit 6 of Miscellaneous 5 Register, Index B3h. Bits 4 and 5 control wait states when fast ROMCS is enabled. For more information, see Table 66, "DOS ROM and Fast DOS ROM Read/Write 16Bit Cycles (See Figure 49)," on page 124. Also see the ElanTMSC300 and ElanTMSC310 Devices' ISA Bus Anomalies Application Note, order #20747.
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
t2a t2b SA23-SA0 t1a ROMCS t1b t14 t4a t4b t8 t6 t3a t3b t15
t5a t5b
MEMR/W
t7 RDDATA t9 WRDATA t10 DBUFOE t12 ENDIRH, ENDIRL 0 = Read t13 t11a t11b
Figure 47. BIOS ROM Read/Write 8-Bit Cycle
ElanTMSC300 Microcontroller Data Sheet
121
PRELIMINARY Table 65. DOS ROM Read/Write 8-Bit Cycle (See Figure 48)
Preliminary Symbol t1a t1b t2a t2b t3a t3b t4a t4b t5a t5b t6 t7 t8 t9 t10 t11a t11b t12 t13 t14 t15 Parameter Description SA stable to DOSCS active SA stable to DOSCS active SA hold from DOSCS inactive (write) SA hold from DOSCS inactive (read) DOSCS pulse width (read) DOSCS pulse width (write) MEMW active to DOSCS active MEMR active to DOSCS active DOSCS hold from MEMW inactive DOSCS hold from MEMR inactive RDDATA setup to command inactive RDDATA hold from command inactive WRDATA setup to command inactive WRDATA hold from command inactive DBUFOE active from command DBUFOE hold from MEMW DBUFOE hold from MEMR ENDIRH, ENDIRL setup to MEMR ENDIRH, ENDIRL hold from MEMR DOSCS active to command active DOSCS hold from SA 2 2 -3 170 5 50 -2 50 Notes 1 2 1 1 1 1 1 1 1 1 40 0 90 50 5 50 0 550 500 4 4 0 0 Min 160 5 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. This is the timing when DOSCS is qualified with MEMR or MEMW, (Bit 4 of ROM Configuration 3 Register, Index B8h, = 0). 2. This is the timing when DOSCS is configured as an address decode, (Bit 4 of ROM Configuration 3 Register, Index B8h, = 1). These timings are based on default settings with bit 2 in Index 50h set to 0 and bits 0 and 1 in Index 62h equal to 0 for 5 wait states, and required initial programming. These timings may be modified via the MMS Memory Wait State 1 Register, Index 62h, the Command Delay Register, Index 60h, and the MMS Memory Wait State 2 Register Index 50h. (See the ElanTMSC300 Microcontroller Programmer's Reference Manual, order #18470.)
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
t2a t2b
SA19-SA0
t3a t3b t1a
t15
DOSCS
t1b
t14 t4a t4b
t8 t6 t5a t5b
MEMR/W
t7
RDDATA
t9
WRDATA
t10
t11a t11b
DBUFOE
t12
t13 0 = Read
ENDIRH, ENDIRL
Figure 48. DOS ROM Read/Write 8-Bit Cycle
ElanTMSC300 Microcontroller Data Sheet
123
PRELIMINARY Table 66. DOS ROM and Fast DOS ROM Read/Write 16-Bit Cycles (See Figure 49)
Standard DOS ROM Preliminary Min t1a t1b t2a t2b t3a t3b t4a t4b t5a t5b t6 t7 t8 t9 t10 t11a t11b t12 t13 t14 t15 t16a t16b SA stable to DOSCS active SA stable to DOSCS active SA hold from DOSCS inactive (write) SA hold from DOSCS inactive (read) DOSCS pulse width (read) DOSCS pulse width(write) MEMW active to DOSCS active MEMR active to DOSCS active DOSCS hold from MEMW inactive DOSCS hold from MEMR inactive RDDATA setup to command inactive RDDATA hold from command inactive WRDATA setup to command inactive WRDATA hold from command inactive DBUFOE active from command DBUFOE hold from MEMW DBUFOE hold from MEMR ENDIRH, ENDIRL setup to MEMR ENDIRH, ENDIRL hold from MEMR DOSCS active to command active DOSCS hold from SA MEMR pulse width MEMW pulse width 2 2 50 -2 50 -4 65 5 550 500 1 2 1 1 1 1 1 1 1 1 0 0 25 0 400 45 5 15 -2 15 -4 15 5 130 100 50 0 550 500 3 4 0 0 25 0 120 15 5 20 0 20 -4 20 5 250 175 65 5 15 0 130 100 3 4 0 0 33 0 160 20 0 Max Fast DOS 33 MHz Preliminary Min 25 5 20 0 250 175 3 4 Max Fast DOS 25 MHz Preliminary Min 25 8 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Symbol
Parameter Description
Notes
Units
Notes: 1. This is the timing when DOSCS is qualified with MEMR or MEMW, (Bit 4 of ROM Configuration 3 Register, Index B8h, = 0). 2. This is the timing when DOSCS is configured as an address decode, (Bit 4 of ROM Configuration 3 Register, Index B8h, = 1). These timings are based on Index 51h, bit 1 set for 16-bit DOSCS cycles, and required initial programming. The standard DOS ROM timings are based on the default wait state settings in bits 2 and 3 of the MMS Memory Wait State Register, Index 62h, set to 4 wait states. The fast DOS ROM timings are based on Index B8h, bit 7 set for DOSCS cycles to run at high-speed with the default setting in bits 5 and 6 for 4-wait states. These timings may be modified via the Command Delay Register, Index 60h. (See the ElanTMSC310 Microcontroller Programmer's Reference Manual, order #18470.) For more information about fast DOS ROM cycles, see the ElanTMSC300 and ElanTMSC310 Devices' ISA Bus Anomalies Application Note, order #20747. The fast DOS ROM timings shown here also apply to fast BIOS ROM (ROMCS) accesses controlled by Miscellaneous 5 Register, Index B3h.
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
t2a t2b
SA23-SA0
t3a t3b t1a
t15
DOSCS
t1b t16a,b t4a t4b t8 t6 t5a t5b
t14
MEMR/W
t7
RDDATA
t9
WRDATA
t10
DBUFOE
t11a t11b
t12
t13 0 = Read
ENDIRH, ENDIRL
Figure 49.
DOS ROM Read/Write 16-Bit Cycle
ElanTMSC300 Microcontroller Data Sheet
125
PRELIMINARY
:
Table 67.
ISA Memory Read/Write 8-Bit Cycle (See Figure 50)
Preliminary
Symbol t1 t2 t3 t4 t5a t5b t6 t7a t7b t8a t8b t9a t9b t10 t11 t12 t13 t14 t15a t15b t16 t17 t18 t19
Parameter Description LA stable to BALE inactive SA stable to command active BALE pulse width LA hold from BALE inactive SA hold from command inactive write SA hold from command inactive read BALE inactive to command active MEMW command pulse width MEMR command pulse width MEMW active to IOCHRDY inactive MEMR active to IOCHRDY inactive MEMW hold from IOCHRDY active MEMR hold from IOCHRDY active RDDATA setup to command inactive RDDATA hold from command inactive WRDATA setup to command inactive WRDATA hold from command inactive DBUFOE active from command DBUFOE hold from MEMW DBUFOE hold from MEMR ENDIRH, ENDIRL setup to MEMR ENDIRH, ENDIRL hold from MEMR LA stable to SA stable SA stable to BALE inactive
Notes
Min 60 160 35 40 50 0
Max
Units ns ns ns ns ns ns
140 500 550 340 340 110 160 40 0 300 50 5 50 -2 170 -4 15 45
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: These timings are based on default settings and required initial programming. These timings may be modified via the MMS Memory Wait State1 Register, Index 62h, and the Command Delay Register, Index 60h. (See the ElanTMSC300 Microcontroller Programmer's Reference Manual, order #18470.)
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
t1 t3
BALE
t19 t4
LA23-LA17
t18
SA23-SA0
t5a t5b
t7a t7b t6 t2 t12 t10
MEMR/W
t8a t8b
IOCHRDY
t9a t9b
t11
RDDATA
t13
WRDATA
t14
DBUFOE
t15a t15b
ENDIRH, ENDIRL
t16 0 = Read
t17
Figure 50. ISA Memory Read/Write 8-Bit Cycle
ElanTMSC300 Microcontroller Data Sheet
127
PRELIMINARY Table 68. ISA Memory Read/Write 16-Bit Cycle (See Figure 51)
Preliminary Symbol t1 t2 t3 t4 t5a t5b t6 t7a t7b t8a t8b t9a t9b t10a t10b t11 t12 t13 t14 t15 t16a t16b t17 t18 t19 t20 t21 Parameter Description LA stable to BALE inactive SA stable to command active BALE pulse width LA hold from BALE inactive SA hold from command inactive write SA hold from command inactive read BALE inactive to command active LA stable to MCS16 valid MCS16 hold from LA change MEMW command pulse width MEMR command pulse width MEMW active to IOCHRDY inactive MEMR active to IOCHRDY inactive MEMW hold from IOCHRDY active MEMR hold from IOCHRDY active RDDATA setup to command inactive RDDATA hold from command inactive WRDATA setup to command inactive WRDATA hold from command inactive DBUFOE active from command DBUFOE hold from command write DBUFOE hold from command read ENDIRH, ENDIRL setup to MEMR ENDIRH, ENDIRL hold from MEMR SA (23:13) stable to MCS16 valid LA stable to SA stable SA stable to BALE inactive 15 45 50 -2 50 -4 25 25 0 330 50 5 0 500 550 340 340 110 160 Notes Min 60 70 35 40 50 0 30 35 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: These timings are based on default settings and required initial programming. These timings may be modified via the MMS Memory Wait State 1 Register, Index 62h, and the Command Delay Register, Index 60h. (See the ElanTMSC300 Microcontroller Programmer's Reference Manual, order #18470.)
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
t1 t3
BALE
t21 t4
LA23-LA17
t20 t5a t5b
SA23-SA0
t8a t8b t6 t2 t13 t11
MEMR/W
t7a t7b
MCS16
t9a t9b t10a t10b
IOCHRDY
t12
RDDATA
t14
WRDATA
t15 t16a t16b
DBUFOE
t17 t18 0 = Read
ENDIRH, ENDIRL
Figure 51.
ISA Memory Read/Write 16-Bit Cycle
ElanTMSC300 Microcontroller Data Sheet
129
PRELIMINARY
Table 69. ISA Memory Read/Write 0 Wait State Cycle (See Figure 52)
Preliminary Symbol t1 t2 t3 t4 t5a t5b t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 Parameter Description LA stable to BALE inactive SA stable to command active BALE pulse width LA hold from BALE inactive SA hold from command inactive write SA hold from command inactive read BALE inactive to command active LA stable to MCS16 active Command pulse width Command active to 0WS active 0WS hold from command inactive MCS16 hold from LA change RDDATA setup to command inactive RDDATA hold from command inactive WRDATA setup to command inactive WRDATA hold from command inactive 1 0 25 0 100 -1 100 0 20 40 Notes Min 60 70 35 40 0 0 30 35 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. If the data bus is externally buffered and/or level translated, this write data hold time will be increased by the propagation delay through the buffer and/or the output disable delay of the buffer. These timings are based on default settings and required initial programming. These timings may be modified via the MMS Memory Wait State 1 Register, Index 62h, and the Command Delay Register, Index 60h. (See the ElanTMSC300 Microcontroller Programmer's Reference Manual, order #18470.)
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
t1 t3
BALE
t4
LA23-LA17
t5a t5b
SA23-SA0
t8 t6 t2 t14 t12
MEMR/W
t7
t11
MCS16
t9
t10
0WS
t13
RDDATA
t15
WRDATA
Figure 52.
ISA Memory Read/Write 0 Wait State Cycle
ElanTMSC300 Microcontroller Data Sheet
131
PRELIMINARY
Table 70.
ISA I/O 8-Bit Read/Write Cycle (See Figure 53)
Preliminary
Symbol t1a t1b t2a t2b t3a t3b t4a t4b t5a t5b t6 t7 t8 t9 t10 t11a t11b t12 t13 t14
Parameter Description SA stable to IOW active SA stable to IOR active SA hold from IOW inactive SA hold from IOR inactive IOW pulse width IOR pulse width IOW active to IOCHRDY inactive IOR active to IOCHRDY inactive IOW hold from IOCHRDY active IOR hold from IOCHRDY active RDDATA setup to command inactive RDDATA hold from command inactive WRDATA setup to command inactive WRDATA hold from command inactive DBUFOE active from command DBUFOE hold from command write DBUFOE hold from command read ENDIRH, ENDIRL setup to IOR ENDIRH, ENDIRL hold from IOR BALE pulse width
Notes
Min 200 150 50
Max
Units ns ns ns ns ns ns
1
50 450
1
505 300 350 110 160 40 0 400 50 5 50
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1
50 150
1
50 50
Notes: 1. These timings apply only to the B4 version of the ELANSC300 microcontroller. The timings for the B3 version are t2b = 0 ns, t3b = 550 ns, t11b = -2 ns, and t13 = -4 ns. These timings may be modified via the MMS Memory Wait State 1 Register, Index 62h, and the Command Delay Register, Index 60h. (See the ElanTMSC300 Microcontroller Programmer's Reference Manual, order #18470.)
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
t2a t2b
SA15-SA0
BALE
t14 t3a t3b t8 t6 t1a t1b t5a t5b
IOR/W
t4a t4b
IOCHRDY
t7
RDDATA
t9
WRDATA
t10
t11a t11b
DBUFOE
t12
t13 0 = Read
ENDIRH, ENDIRL
Figure 53.
ISA I/O 8-Bit Read/Write Cycle
ElanTMSC300 Microcontroller Data Sheet
133
PRELIMINARY Table 71. ISA I/O 16-Bit Read/Write Cycle (See Figure 54)
Preliminary Symbol t1a t1b t2 t3a t3b t4a t4b t5a t5b t6a t6b t7 t8 t9 t10 t11 t12a t12b t13 t14 t15 Parameter Description SA stable to IOW active SA stable to IOR active SA stable to IOCS16 active IOW active to IOCHRDY inactive IOR active to IOCHRDY inactive IOW hold from IOCHRDY active IOR hold from IOCHRDY active IOW pulse width IOR pulse width SA hold from IOW inactive SA hold from IOR inactive RDDATA setup to command inactive RDDATA hold from command inactive WRDATA setup to command inactive WRDATA hold from command inactive DBUFOE active from command DBUFOE hold from command write DBUFOE hold from command read ENDRIH, ENDIRL setup to IOR ENDIRH, ENDIRL hold from IOR BALE pulse width 1 1 50 50 100 50 50 1 1 110 160 160 225 50 50 40 0 250 50 5 Notes Min 200 150 95 30 80 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. These timings apply to the B4 version of the ELANSC300 microcontroller only. The timings for the B3 version are t5b = 260, t6b = 0, t12b = -2 ns, and t14 = -4 ns. These timings are based on default settings and required initial programming. These timings may be modified via the MMS Memory Wait State1 Register, Index 62h, and the Command Delay Register, Index 60h. (See the ElanTMSC300 Microcontroller Programmer's Reference Manual, order #18470.)
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
t6a t6b
SA15-SA0
BALE
t15 t5a t5b t1a t1b t13 t9 t7
IOR/W
t2
t4a t4b
IOCS16
t3a t3b
IOCHRDY
t8
RDDATA
t10
WRDATA
t11
DBUFOE
t12a t12b
t14
ENDIRH, ENDIRL Figure 54.
0 = Read
ISA I/O 16-Bit Read/Write Cycle
ElanTMSC300 Microcontroller Data Sheet
135
PRELIMINARY Table 72. EPP Data Register Write Cycle (See Figure 55)
Symbol t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 Parameter Description AFDT delay from IOW active AFDT delay from PPDCS active AFDT delay from PPOEN active AFDT active pulse width (no wait states added) AFDT High to Low recovery AFDT Low to STRB Low STRB delay from PPDCS active STRB delay from PPOEN active AFDT High to STRB High delay STRB Low to data valid delay STRB High to data valid hold PPOEN delay from IOW active PPOEN delay from IOW inactive PPDCS delay from IOW active PPDCS delay from IOW inactive AFDT hold from BUSY High BUSY Low delay from AFDT active 139 307 6.6 4.3 129 7.4 1.1 Max 8.4 1.8 1.0 450 1000 -0.2 1.6 0.8 -2.4 3.7 4.0 0.9 0.6 -1.4 Min 4.9 1.1 0.8 448 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: The appropriate timings above are valid for the Bidirectional Parallel Port mode also. Timings t13 and t14 are also valid for the Unidirectional Parallel Port mode. (PPDCS is PPWDE in Unidirectional mode.)
t0 t2 t1 t15 t3 t4
AFDT
t5 t6 t7
STRB
t9 t10 Valid Data t16
t8
D7-D0
BUSY
t11
PPOEN
t13
t12
PPDCS IOW IOR
t14
Figure 55.
EPP Data Register Write Cycle
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY Table 73.
Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9
EPP Data Register Read Cycle (See Figure 56)
Parameter Description Max 1.8 450 1000 25.3 2.3 6.8 3.7 1.8 4.2 0 Min 1.1 448 Unit ns ns ns ns ns ns ns ns ns
AFDT delay from PPDCS active AFDT active pulse width (no wait states) AFDT High to Low recovery Read data valid delay Read data hold time PPDCS delay from IOR active PPDCS delay from AFDT inactive PPDCS delay from IOR inactive BUSY (inactive) hold from AFDT High
Notes: The appropriate timings above are also valid for the Bidirectional Parallel Port mode.
t1 t2 t3
AFDT STRB
t4 t5 Data Valid t7 t6 t8
D7-D0
PPDCS PPOEN IOR IOW
t9
BUSY Figure 56. EPP Data Register Read Cycle
ElanTMSC300 Microcontroller Data Sheet
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PRELIMINARY
PHYSICAL DIMENSIONS PQR 208, Trimmed and Formed Plastic Shrink Quad Flat Pack (QFP)
Pin 208 25.50 REF
27.90 28.10
30.40 30.80
Pin 156
Pin 1 I.D.
25.50 REF 27.90 28.10 30.40 30.80
Pin 52 Pin 104 3.20 3.60 0.25 MIN 0.50 BASIC 3.95 MAX
SEATING PLANE
Notes: 1. All measurements are in millimeters unless otherwise noted. 2. Not to scale. For reference only.
16-038-PQR-1_AH PQR208 EC95 8-13-97 lv
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ElanTMSC300 Microcontroller Data Sheet
PRELIMINARY
PHYSICAL DIMENSIONS (CONTINUED) PQL 208, Trimmed and Formed Thin Quad Flat Pack (TQFP)
208
1
29.80 27.80 30.20 28.20
52
27.80 28.20 29.80 30.20
11 - 13 1.35 1.45 1.60 MAX
16-038-PQT-1_AL PQL208 9.4.97 lv
0.50 BSC 1.00 REF.
11 - 13
Notes: 1. All measurements are in millimeters unless otherwise noted. 2. Not to scale. For reference only.
Trademarks AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Am386 and Am486 are registered trademarks of Advanced Micro Devices, Inc. E86, K86, and Elan are trademarks of Advanced Micro Devices, Inc. FusionE86 is a service mark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
ElanTMSC300 Microcontroller Data Sheet
139

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